Intel NETWORK PROCESSOR IXP2800 - Manual (Page 308)

308 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
The SPI-4.2 interface does not support a virtual output queue (VOQ) flow control mechanism.
The Intel
® IXP2800 Network Processor supports use of the CSIX-L1 protocol-based flow control
interface (as used in the dual chip, full-duplex configuration) on the ingress network processor,
while SPI-4.2 is operational on the data interface. This interface can provide VOQ flow control
information from the fabric and allow the transmitter scheduler, implemented in a Microengine
within the ingress network processor, to avoid sending data bursts to congested destinations.
The fabric should send alternating Idle CFrames and Dead Cycles when there are no Flow Control
CFrames to transmit. The CRdy and DRdy “ready bits” should be set to 0 on transmission and are
ignored on reception.
The fabric should respond to the RXCFC backpressure signal. In this mode of operation, the
RXCSRB signal that would normally receive the state of the CRdy and DRdy “ready bits” is not
used. If dynamic de-skew is configured on the interface, and the backpressure signal is asserted for
32 clock cycles, the fabric sends a (de-skew) training sequence on the flow control interface. It may
be acceptable in this configuration to operate the flow control interface at a sufficiently low clock
rate that dynamic de-skew is not required.
Operation in the hybrid simplex mode for the ingress network processor is slightly more taxing on
the transmit scheduler computation than the homogenous CSIX-L1 protocol configurations. The
status reported for the data interface must be polled by the transmit scheduler. In this configuration,
the response to link-level flow control is performed in software and is slower than in the
homogenous CSIX-L1 protocol configurations where it is accomplished in hardware.
8.9.4.2.5
Support for Dynamic De-Skew Training
The SPI-4.2 interface incorporates a training sequence for dynamic de-skew of its signals relative
to the source synchronous clock. This training sequence has been extended and incorporated into
the CSIX-L1 protocol support of the Intel ® IXP2800 Network Processor.
The training pattern for the 16-bit data interface consists of 20 words, 10 repetitions of 0x0fff
followed by 10 repetitions of 0xf000. The CTL and PAR signals are asserted for the first 10 words
and de-asserted for the second 10 words. The PROT signal (see below) is de-asserted for the first
10 words and asserted for the second 10 words. A training sequence consists of “alpha” repetitions
of the training pattern. The idle control word that precedes a training sequence in SPI-4.2 is not
used in conjunction with the CSIX-L1 protocol. See
Section 8.6.1 for more information.
A receiver should detect a training sequence in the context of the CSIX-L1 protocol
implementation by the assertion of the start-of-frame signal for three adjacent clock edges and the
correct value on the data signals for those three adjacent clock edges.
A receiver may request a training sequence to be sent by transmitting continuous Dead Cycles on
the interface. Reception of two adjacent Dead Cycles triggers the transmission of a training
sequence in the opposite direction. If an interface is sending Dead Cycles and a training sequence
becomes pending, the interface must send the training sequence at a higher priority than the Dead
Cycles. Otherwise, a deadlocked situation may arise.
In the simplex configuration, the request for training, and the response to it, occur between a
primary interface and its associated reverse path control interface. In the dual chip, full-duplex
configuration, requests for training and Dead Cycles are encoded across the flow control interface
as either continuous Dead Cycles or continuous Idle CFrames, both of which violate the standard
CSIX-L1 protocol.