Intel NETWORK PROCESSOR IXP2800 User Manual
Page 13
Hardware Reference Manual
13
Contents
Command Bus Master Access to Local Configuration Registers ........345
Command Bus Master Access to Local Control and
Command Bus Master Direct Access to PCI Bus ................................346
9.4.2.3.1 PCI Address Generation for IO and MEM Cycles................346
9.4.2.3.2 PCI Address Generation for Configuration Cycles...............347
9.4.2.3.3 PCI Address Generation for Special and IACK Cycles........347
9.4.2.3.4 PCI Enables .........................................................................347
9.4.2.3.5 PCI Command .....................................................................347
Target Access Has an Address Parity Error ........................................348
Initiator Asserts PCI_PERR_L in Response to One of Our Data
Discard Timer Expires on a Target Read.............................................348
Target Access to the PCI_CSR_BAR Space Has Illegal
Target Write Access Receives Bad Parity PCI_PAR with the Data.....349
SRAM Responds with a Memory Error on One or More Data Phases
DRAM Responds with a Memory Error on One or More Data Phases
DMA Read from DRAM (Memory-to-PCI Transaction) Gets a
DMA Read from SRAM (Descriptor Read) Gets a Memory Error ........350
DMA from DRAM Transfer (Write to PCI) Receives PCI_PERR_L on
DMA To DRAM (Read from PCI) Has Bad Data Parity .......................350
DMA Transfer Experiences a Master Abort (Time-Out) on PCI ...........351
DMA Transfer Receives a Target Abort Response During a
DMA Descriptor Has a 0x0 Word Count (Not an Error) .......................351
As a PCI Initiator During a Direct Access from the Intel
Master Transfer Experiences a Master Abort (Time-Out) on PCI ........351
Master Transfer Receives a Target Abort Response During
Master from the Intel XScale® Core or Microengine Transfer
(Write to PCI) Receives PCI_PERR_L on PCI Bus .............................352
Master Read from PCI (Read from PCI) Has Bad Data Parity ............352
Master Transfer Receives PCI_SERR_L from the PCI Bus ................352
Intel XScale® Core Microengine Requests Direct Transfer when
the PCI Bus is in Reset ........................................................................352
PCI Data Byte Lane Alignment .........................................................................................352
9.6.1
Clocks and Reset.......................................................................................................................359
10.1 Clocks ...............................................................................................................................359
10.2 Synchronization Between Frequency Domains ................................................................363
10.3 Reset ................................................................................................................................364
10.3.1 Hardware Reset Using nRESET or PCI_RST_L .................................................364