Intel NETWORK PROCESSOR IXP2800 - Manual (Page 54)

54 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
2.5.4 Queue Data Structure Commands
The ability to enqueue and dequeue data buffers at a fast rate is key to meeting line-rate
performance. This is a difficult problem as it involves dependent memory references that must be
turned around very quickly. The SRAM controller includes a data structure (called the Q_array)
and associated control logic to perform efficient enqueue and dequeue operations. The Q_array has
64 entries, each of which can be used in one of four ways.
• Linked-list queue descriptor (resident queues)
• Cache of recently used linked-list queue descriptors (backing store for the cache is in SRAM)
• Ring descriptor
• Journal
The commands provided are:
For Linked-list queues or Cache of recently used linked-list queue descriptors
• Read_Q_Descriptor_Head(address, length, entry, xfer_addr)
• Read_Q_Descriptor_Tail(address, length, entry)
• Read_Q_Descriptor_Other(address, entry)
• Write_Q_Descriptor(address, entry)
• Write_Q_Descriptor_Count(address, entry)
• ENQ(buff_desc_adr, cell_count, EOP, entry)
• ENQ_tail(buff_desc_adr, entry)
• DEQ(entry, xfer_addr)
For Rings
• Get(entry, length, xfer_addr)
• Put(entry, length, xfer_addr)
For Journals
• Journal(entry, length, xfer_addr)
• Fast_journal(entry)
Note: The Read_Q_Descriptor_Head, Read_Q_Descriptor_Tail, etc.) are used to initialize the rings and
journals but not used to perform the ring and journal function.
2.5.5 Reference Ordering
This section covers the ordering between accesses to any one SRAM controller.
2.5.5.1 Reference Order Tables
Table 12 shows the architectural guarantees of order to access to the SAME SRAM address
between a reference of any given type (shown in the column labels) and a subsequent reference of
any given type (shown in the row labels). The definition of first and second is defined by the order
they are received by the SRAM controller.
Note: A given Network Processor version may implement a superset of these order guarantees. However,
that superset may not be supported in future implementations.