Intel NETWORK PROCESSOR IXP2800 - Manual (Page 9)

Hardware Reference Manual 9
Contents
6.2.1 Internal Interface ..................................................................................................209
6.2.2 Number of Channels ............................................................................................209
6.2.3 Coprocessor and/or SRAMs Attached to a Channel............................................209
6.3 SRAM Controller Configurations.......................................................................................209
6.4 Command Overview .........................................................................................................211
6.4.1
Basic Read/Write Commands..............................................................................211
6.4.2 Atomic Operations ...............................................................................................211
6.4.3 Queue Data Structure Commands ......................................................................213
6.4.3.1
Read_Q_Descriptor Commands..........................................................216
6.4.3.2 Write_Q_Descriptor Commands ..........................................................216
6.4.3.3 ENQ and DEQ Commands ..................................................................217
6.4.4 Ring Data Structure Commands ..........................................................................217
6.4.5 Journaling Commands.........................................................................................217
6.4.6 CSR Accesses .....................................................................................................217
6.5 Parity.................................................................................................................................217
6.6 Address Map.....................................................................................................................218
6.7 Reference Ordering ..........................................................................................................219
6.7.1
Reference Order Tables ......................................................................................219
6.7.2 Microcode Restrictions to Maintain Ordering .......................................................220
6.8 Coprocessor Mode ...........................................................................................................221
7 SHaC — Unit Expansion ...........................................................................................................225
7.1
Overview...........................................................................................................................225
7.1.1
SHaC Unit Block Diagram....................................................................................225
7.1.2 Scratchpad...........................................................................................................227
7.1.2.1
Scratchpad Description........................................................................227
7.1.2.2 Scratchpad Interface............................................................................229
7.1.2.2.1 Command Interface .............................................................229
7.1.2.2.2 Push/Pull Interface...............................................................229
7.1.2.2.3 CSR Bus Interface ...............................................................229
7.1.2.2.4 Advanced Peripherals Bus Interface (APB) .........................229
7.1.2.3 Scratchpad Block Level Diagram.........................................................229
7.1.2.3.1 Scratchpad Commands .......................................................230
7.1.2.3.2 Ring Commands ..................................................................231
7.1.2.3.3 Clocks and Reset.................................................................235
7.1.2.3.4 Reset Registers ...................................................................235
7.1.3 Hash Unit .............................................................................................................236
7.1.3.1
Hashing Operation ...............................................................................237
7.1.3.2 Hash Algorithm ....................................................................................239
8 Media and Switch Fabric Interface...........................................................................................241
8.1
Overview...........................................................................................................................241
8.1.1
SPI-4....................................................................................................................243
8.1.2 CSIX ....................................................................................................................246
8.1.3 CSIX/SPI-4 Interleave Mode................................................................................246
8.2 Receive.............................................................................................................................247
8.2.1
Receive Pins........................................................................................................248
8.2.2 RBUF ...................................................................................................................248
8.2.2.1
SPI-4 ....................................................................................................250
8.2.2.2 CSIX.....................................................................................................253
8.2.3 Full Element List ..................................................................................................255
8.2.4 Rx_Thread_Freelist_# .........................................................................................255