Intel NETWORK PROCESSOR IXP2800 - Manual (Page 77)

Hardware Reference Manual 77
Intel
®
IXP2800 Network Processor
Technical Description
2.11.2 Timers
The IXP2800 Network Processor contains four programmable 32-bit timers, which can be used for
software support. Each timer can be clocked by the internal clock, by a divided version of the
clock, or by a signal on an external GPIO pin. Each timer can be programmed to generate a
periodic interrupt after a programmed number of clocks. The range is from several ns to several
minutes depending on the clock frequency.
In addition, timer 4 can be used as a watchdog timer. In this use, software must periodically reload
the timer value; if it fails to do so and the timer counts to 0, it will reset the chip. This can be used
to detect if software “hangs” or for some other reason fails to reload the timer.
2.11.3 General Purpose I/O
The IXP2800 Network Processor contains eight General Purpose I/O (GPIO) pins. These can be
programmed as either input or output and can be used for slow speed I/O such as LEDs or input
switches. They can also be used as interrupts to the Intel XScale ® core, or to clock the
programmable timers.
2.11.4 Universal Asynchronous Receiver/Transmitter
The IXP2800 Network Processor contains a standard RS-232 compatible Universal Asynchronous
Receiver/Transmitter (UART), which can be used for communication with a debugger or
maintenance console. Modem controls are not supported; if they are needed, GPIO pins can be
used for that purpose.
The UART performs serial-to-parallel conversion on data characters received from a peripheral
device and parallel-to-serial conversion on data characters received from the processor. The
processor can read the complete status of the UART at any time during operation. Available status
information includes the type and condition of the transfer operations being performed by the
UART and any error conditions (parity, overrun, framing or break interrupt).
The serial ports can operate in either FIFO or non-FIFO mode. In FIFO mode, a 64-byte transmit
FIFO holds data from the processor to be transmitted on the serial link and a 64-byte receive FIFO
buffers data from the serial link until read by the processor.
The UART includes a programmable baud rate generator that is capable of dividing the internal
clock input by divisors of 1 to 2
16 - 1 and produces a 16X clock to drive the internal transmitter
logic. It also drives the receive logic. The UART can be operated in polled or in interrupt driven
mode as selected by software.
2.11.5 Slowport
The Slowport is an external interface to the IXP2800 Network Processor, used for Flash ROM
access and 8, 16, or 32-bit asynchronous device access. It allows the Intel XScale ® core do read/
write data transfers to these slave devices.
The address bus and data bus are multiplexed to reduce the pin count. In addition, 24 bits of
address are shifted out on three clock cycles. Therefore, an external set of buffers is needed to latch
the address. Two chip selects are provided.