Intel NETWORK PROCESSOR IXP2800 - Manual (Page 195)

Hardware Reference Manual 195
Intel
®
IXP2800 Network Processor
DRAM
5.6.2 Parity Enabled
On writes, odd byte parity is computed for each byte and written into the corresponding parity bit.
Partial writes (writes of less than eight bytes) are done as masked writes.
On reads, odd byte parity is computed on each byte of data and compared to the corresponding
parity bit. If there is an error RDRAMn_Error_Status_1[Uncorr_Err] bit is set, which can interrupt
the Intel XScale
® core if enabled. The Data Error signal will be asserted when the read data is
delivered on D_Push_Data.
The address of the error, along with other information, is logged in
RDRAMn_Error_Status_1[ADDR] and RDRAMn_Error_Status_2. Once the error bit is set, those
registers are locked. That is, the information relating to subsequent errors is not loaded until the
error status bit is cleared by the Intel XScale ® core write.
5.6.3 ECC Enabled
On writes, eight ECC check bits are computed based on 64 bits of data, and are written into the
check bits. Partial writes (writes of less than eight bytes) cause the channel controller to do a
read-modify-write. Any single-bit error detected during the read portion is corrected prior to
merging with the write data. An uncorrectable error detected during the read does not modify the
data. Either type of error will set the appropriate error status bit, as described below.
On reads, the correct value for the check bits is computed from the data and is compared to the
ECC check bits. If there is no error, data is delivered to the originator of the read, because it came
from the RDRAMs. If there is a single-bit error, it is corrected before being delivered (the
correction is done automatically, the reader is given the correct data). The error is also logged by
setting the RDRAMn_Error_Status_1[Corr_Err] bit, which can interrupt the Intel XScale ® core if
enabled.
If there is an uncorrectable error, the RDRAMn_Error_Status_1[Uncorr_Err] bit is set, which can
interrupt the Intel XScale
®
core if enabled. The Data Error signal is asserted when the read data is
delivered on D_Push_Data, unless the token, Ignore Data Error, was asserted in the command. In
that case, the RDRAM controller does not assert Data Error and does not assert a Signal (it will use
0xF, which is a null signal, in place of the requested signal number).
In both correctable and uncorrectable cases, the address of the error, along with other information,
is logged in RDRAMn_Error_Status_1[ADDR] and RDRAMn_Error_Status_2. Once either of the
error bits is set, those registers are locked. That is, the information relating to subsequent errors is
not loaded until both error status bits are clear. That does not prevent the correction of single-bit
errors, only the logging.
Note: When a single-bit error is corrected, the corrected data is not written back into memory (scrubbed)
by hardware; this can be done by software if desired, because all of the information pertaining to
the error is logged.