Intel NETWORK PROCESSOR IXP2800 - Manual (Page 151)

Hardware Reference Manual 151
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
3.12.7.7.1 Mode 1: 16-Bit Microprocessor Interface Support with
16-Bit Address Lines
The address size control register is programmed to 16-bit address space for this case. This mode is
designated for the devices with the similar protocol with the Lucent* TDAT042G5 SONET/SDH
device.
16-Bit Microprocessor Interfacing Topology with 16-Bit address lines
Figure 42 shows a solution for the 16-bit microprocessor interface. This solution bridges the
Lucent* TDAT042G5 SONET/SDH 16-bit interface. From Figure 42 , we observe that the control
pins SP_RD_L and SP_WR_L are converted to R/W and ADS. The CS and DT are still
compactible with SP_CS_L[1] and SP_ACK_L protocol.
Extra pins are added to accomplish the task of multiplexing and demultiplexing the data bus. The
total pin count is 18.
During the write cycle, 8-bit data are stacked into 16-bit data. They are first shifted into two
tri-state buffers, 74F646 or equivalent by SP_CP, using two consecutive clock cycle; then the
SP_CS_L is used for output of the 16-bit data, which is shared with the CS.
During the read cycle, the 16-bit data are unpacked into 8-bit data by SP_CP. Two 74F646 or
equivalent tri-state buffers are used. First, the 16-bit data are stored into these buffers. Then they
are shifted out by SP_DIR, using two consecutive clock cycles.