Intel NETWORK PROCESSOR IXP2800 - Manual (Page 367)

Hardware Reference Manual 367
Intel
®
IXP2800 Network Processor
Clocks and Reset
10.3.3.1 Slave Network Processor (Non-Central Function)
• If the Watchdog timer reset enable bit set to 1, Watchdog reset will trigger the soft reset
• If the Watchdog timer reset enable bit set to 0, Watchdog reset will trigger the PCI interrupt to
external PCI host (if interrupt is enabled by PCI Outbound Interrupt Mask Register[3]).
External PCI host can check the IXP2800 error status and log the error then reset the Slave
IXP2800 Network Processor only or reset all the PCI devices (assert the PCI_RST_L).
• If the Watchdog history bit is already set when a new watchdog event happens, the Watchdog
timer reset enable bit is disregarded and a soft reset is generated.
10.3.3.2 Master Network Processor (PCI Host, Central Function)
• If the Watchdog timer reset enable bit is set to 1, Watchdog reset will trigger the soft reset and
set the watchdog history bit.
• If the Watchdog timer reset enable bit is set to 0, check the watchdog history bit. If is already
set, generate soft reset. If the watchdog history bit is not set already, watchdog reset will just
set the watchdog history bit and no further action is taken.
10.3.3.3 Master Network Processor (Central Function)
• If the Watchdog timer reset enable bit is set to 0, Watchdog reset will trigger the PCI interrupt
to external PCI host (if interrupt is enabled by PCI Outbound Interrupt Mask Register[3]).
• If the Watchdog history bit is already set when a new watchdog event happens, the Watchdog
timer reset enable bit is disregarded, and a soft reset is generated.
• If the Watchdog timer reset enable bit is set to 1, Watchdog reset will trigger the soft reset.
10.3.4 Software-Initiated Reset
The Intel XScale ® core or external PCI bus master can reset specific functions in the IXP2800
Network Processor by writing to the IXP_RESET0 and IXP_RESET1 registers. All the individual
microengines and specific units can be reset individually in this fashion.
Software reset initiated by the Reset All bit in the IXP_RESET0 register behaves almost the same
as hardware resets in the sense that PLL and rest of the core gets reset. The only difference between
soft reset and hard reset is that a 512-cycle counter is added at the output of the RESET_ALL bit
going to the PLL unit for chip reset generation. The PCI unit in the meantime detects the bus idle
condition and generates a local reset. This local reset is removed once chip reset is generated and
chip reset then takes over the reset function of PCI unit.
Both hardware and software resets (software reset after 512 cycles delay) combined generate
PLL_RST for the PLL logic. During the assertion of PLL_RST, PLL block remains in the bypass
mode and passes the incoming clock directly to the core logic. At this time everyone inside the core
gets the same basic clock. The Clock Control register is reset to 0x0FFF_FFFF using the same
signal.
Once the PLL_RST signal goes away, the PLL starts generating divide_by_2 clock for the
Microengines, divide_by_4 clock for the Intel XScale
®
core and divide_by_16 clock for the rest of
the chip (not using divide_by_4 clock) after inserting 16 – 32 idle clocks. Once the clock control
CSR is written by software, the PLL block detects it by finding a change in value of this register.