Intel NETWORK PROCESSOR IXP2800 User Manual
Page 11
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Hardware Reference Manual
11
Contents
Single IXP2800 Network Processor.....................................................289
Interface to Command and Push and Pull Buses .............................................................290
8.8.1
RBUF or MSF CSR to Microengine S_TRANSFER_IN Register for Instruction:.291
Microengine S_TRANSFER_OUT Register to TBUF or
Receiver and Transmitter Interoperation with Framers and Switch Fabrics .....................292
8.9.1
Simplex Configuration..........................................................................293
Hybrid Simplex Configuration ..............................................................294
Dual Network Processor Full Duplex Configuration.............................295
Single Network Processor Full Duplex Configuration (SPI-4.2) ...........296
Single Network Processor, Full Duplex Configuration
(SPI-4.2 and CSIX-L1) .........................................................................297
System Configurations.........................................................................................297
8.9.2.1
Framer, Single Network Processor Ingress and Egress, and
Fabric Interface Chip............................................................................298
Framer, Dual Network Processor Ingress, Single
Network Processor Egress, and Fabric Interface Chip ........................298
Framer, Single Network Processor Ingress and Egress, and
CSIX-L1 Chips for Translation and Fabric Interface ............................299
CPU Complex, Network Processor, and Fabric Interface Chip ...........299
Framer, Single Network Processor, Co-Processor, and
Fabric Interface Chip............................................................................300
SPI-4.2 Transmitter..............................................................................302
CSIX-L1 Interface Reference Model: Traffic Manager and Fabric
Intel® IXP2800 Support of the CSIX-L1 Protocol ................................304
8.9.4.2.1 Mapping to 16-Bit Wide DDR LVDS ....................................304
8.9.4.2.2 Support for Dual Chip, Full-Duplex Operation .....................305
8.9.4.2.3 Support for Simplex Operation.............................................306
8.9.4.2.4 Support for Hybrid Simplex Operation .................................307
8.9.4.2.5 Support for Dynamic De-Skew Training...............................308
CSIX-L1 Protocol Receiver Support ....................................................309
CSIX-L1 Protocol Transmitter Support ................................................310
Implementation of a Bridge Chip to CSIX-L1 .......................................311
Dual Protocol Receiver Support...........................................................312
Dual Protocol Transmitter Support.......................................................312
Implementation of a Bridge Chip to CSIX-L1 and SPI-4.2 ...................313
SPI-4.2 Transmitter State Machine......................................................314
Training Transmitter State Machine.....................................................315
CSIX-L1 Transmitter State Machine ....................................................315
Summary of Receiver and Transmitter Signals ...................................................317