Intel NETWORK PROCESSOR IXP2800 - Manual (Page 198)

198 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
DRAM
Serial reads are done by the following steps:
1. Read RDRAM_Serial_Command; test Busy bit until it is a 0.
2. Write RDRAM_Serial_Command to start the read.
3. Read RDRAM_Serial_Command; test Busy bit until it is a 0.
4. Read RDRAM_Serial_Data to collect the serial read data.
5.10 RDRAM Controller Block Diagram
The RDRAM controller consists of three pieces. Figure 70 is a simplified block diagram.
Pre_RMC — has the queues for commands, data (both in and out), and interfaces to internal
buses. It checks incoming commands and addresses to determine if they are targeted to the channel,
and if so, enqueues them (if a command splits across two channels, the channel must enqueue the
portion of the command that it owns). It sorts the enqueued commands to RDRAM banks, selects
the command to be executed based on policy to get good bank utilization, and then hands off that
command to RMC. It also arbitrates for refresh and calibration, which it requests RMC to perform.
Pre_RMC also contains the ECC logic, and the CSRs that set size, timing, ECC, etc.
RMC — Rambus* Memory Controller, that handles the pin protocol. It controls all timing
dependencies, pin turnaround, RAS-CAS, RAS-RAS, etc., including bank interactions. RMC
handles all commands in the order that it receives them. RMC is based on the Rambus* RMC.
RAC — Rambus* ASIC Cell, a high-speed parallel-to-serial and serial-to-parallel interface. This
is a hard macro that contains the I/O pads and drivers, DLL, and associated pin interface logic.
The following is a brief explanation of command operation:
Pre_RMC enqueues commands and sends them to RMC. It is responsible for initiating Pull
operations to get Microengine/RBUF/Intel XScale ® core/PCI data into the Pull_Data FIFO. A
write is not eligible to go to RMC until Pre_RMC has all the data in the Pull Data FIFO.
Pre_RMC provides the Full signal to the Command Arbiter to inform it stop allowing RDRAM
commands.
Figure 70. RDRAM Controller Block Diagram
A9729-02
CMD Bus RQ
DQ D_Push Bus
D_Pull Bus
Pre_RMC RMC RAC
Intel ®
IXP2800
Network
Processor
RDRAMs