Intel NETWORK PROCESSOR IXP2800 - Manual (Page 289)

Hardware Reference Manual 289
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.7.2.2 Egress IXP2800 Network Processor
1. On reset, FC_STATUS_OVERRIDE[Ingress_Force_En] is set.
2. The Microengine or the Intel XScale
®
core writes a 1 to MSF_Tx_Control[Transmit_Idle] and
MSF_Tx_Control[Transmit_Enable] so that Idle CFrames with low CReady and DReady bits
are sent over TDAT.
3. The Microengine or the Intel XScale ® core polls on
MSF_Interrupt_Status[Detected_CSIX_FC_Idle] to see when the first Idle CFrame is
received. The Intel XScale
®
core may use the Detected_CSIX_FC_Idle Interrupt if
MSF_Interrupt_Enable[Detected_CSIX_FC_Idle] is set.
4. When the first Idle CFrame is received, the Microengine or the Intel XScale ® core writes a 0
to FC_STATUS_OVERRIDE[Ingress_Force_En] to deactivate SRB Override.
5. The Microengine or the Intel XScale ® core polls on FC_Ingress_Status[TM_CReady] and
FC_Ingress_Status[TM_DReady]. When they are seen active, the Microengine or the Intel
XScale
® core writes a 1 to MSF_Tx_Control[TX_En_CC] and
MSF_Tx_Control[TX_En_CD]. Egress IXP2800 then resumes normal operation. Likewise,
when the Switch Fabric recognizes Idle CFrames with “ready bits” high, it will assume normal
operation.
8.7.2.3 Single IXP2800 Network Processor
Both CSIX startup routines described above will be needed to complete the CSIX startup sequence.
Using Simplex mode on a single IXP2800 with RDAT, TDAT and RXCDAT, TXCDAT using
CSIX, there are essentially two independent CSIX receive and transmit buses.