Intel NETWORK PROCESSOR IXP2800 - Manual (Page 310)

310 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
8.9.4.4 CSIX-L1 Protocol Transmitter Support
The Intel ® IXP2800 Network Processor transmitter support for the CSIX-L1 protocol is similar to
that for SPI-4.2. The transmitter fetches CFrames from transmitter buffers. An entire CFrame must
fit within a single buffer. In the case of SPI-4.2, the array of transmitter buffers operates as a single
ring. In the case of CSIX-L1 protocol support, the array of buffers operates as two rings, one for
data CFrames and another for control CFrames. The partitioning of the transmitter buffers is
configured via MSF_Tx_Control[TBUF_Partition]. The portion of the aggregate transmitter buffer
storage (8 Kbytes) allocated to data CFrames is 75% (6 Kbytes), with the remainder (2 Kbytes)
allocated to control CFrames. The size of the buffers within each partition is independently
configurable to a size of 64, 128, or 256 bytes. The payload size of CFrames sent from the buffers
may vary from 1 to the size of the buffer.
The CSIX-L1 protocol link-level flow control operates directly upon the hardware that processes
the two (control and data) transmitter rings. The transmitter services the two rings in round-robin
order when allowed by link-level flow control. The transmitter transmits Idle CFrames and Dead
Cycles according to the CSIX-L1 protocol if there are no CFrames to transmit.
Virtual output queue flow control is accommodated by a transmit scheduler implemented on a
Microengine. In all three network processor ingress configurations, Flow Control CFrames are
loaded by hardware into the flow control ingress FIFO. Two state bits associated with this FIFO are
distributed to all of the Microengines: (1) the FIFO is non-empty, and (2) the FIFO contains more
than a threshold amount of CFrame 32-bit words (HWM_Control[FCIFIFO_Int_HWM])
Any Microengine can perform transmitter scheduling by sensing the state associated with the flow
control ingress FIFO, using the branch-on-state instruction. If the FIFO is not empty, the transmit
scheduler processes some of the FIFO by performing a read of the FCIFIFO registers.
A single Microengine instruction can perform a block read of up to 16 32-bit words. The data for
the read is likely to arrive after several subsequent scheduling decisions. The scheduler should
incorporate the new information from the newly-read Flow Control CFrame(s) in its later
scheduling decisions. If the FIFO state indicates that the threshold capacity has been exceeded, the
scheduler should suspend further scheduling decisions until the FIFO is sufficiently processed,
otherwise it risks making scheduling decisions with information that is stale.
The responsiveness of the network processor to VOQ flow control depends on the transmit pipeline
length, from transmit scheduler to CFrames on the interface signals. For rates at or above 10 Gb/s,
the pipeline length is likely to be 32 – 64 CFrames, assuming four pipeline stages (schedule, de-
queue, data movement, and transmit) and 8 – 16 CFrames concurrently processed per stage.
In the simplex configuration, the egress network processor can send CFrames over the Reverse
Path Control Interface. The CFrames are loaded into the flow control egress FIFO by performing
writes of 32-bit words to the FCEFIFO registers. The base header, the extension header, the
payload, the padding, and a dummy vertical parity must be written to the FIFO. The transmitter
hardware calculates the actual vertical parity as the CFrame is transmitted.
Note: The transmitter hardware for the transmitter buffers and the flow control egress FIFO expect that
only the Flow Control CFrame type does not have an extension header of 32 bits (all other types
have this header). The hardware disregards the contents of the extension header or the payload.
The limited gather capability described for SPI-4.2 also is available for CFrames. A prefix header
of up to 31 bytes and a disjoint payload is supported. The prefix header may start at an offset of 0 to
7 bytes. The payload may start at an offset of 0 to 7 bytes from the octal-byte boundary following
the end of the prefix header. For more complicated merging or shifting of data within a CFrame,
the data should be passed through a Microengine to perform any arbitrary merging and/or shifting.