Intel NETWORK PROCESSOR IXP2800 - Manual (Page 223)

Hardware Reference Manual 223
Intel
®
IXP2800 Network Processor
SRAM Interface
There can be multiple operations in progress in the coprocessor. The SRAM controller sends
parameters to the coprocessor in response to each SRAM write instruction without waiting for
return results of previous writes. If the coprocessor is capable of re-ordering operations — i.e.,
returning the results for a given operation before returning the results of an earlier arriving
operation — Microengine code must manage matching results to operations. Tagging the operation
by putting a sequence value into the parameters, and having the coprocessor copy that value into
the results is one way to accomplish this requirement.
Flow control is under the Network Processor’s Microengine control. A Microengine thread
accessing a coprocessor port maintains a count of the number of entries in that coprocessor’s write-
FIFO port. Each time an entry is written to that coprocessor port, the count is incremented. When a
valid entry is read from that coprocessor read-port, the count is decremented by the thread.