Intel NETWORK PROCESSOR IXP2800 - Manual (Page 65)

Hardware Reference Manual 65
Intel
®
IXP2800 Network Processor
Technical Description
2.7.4 Transmit
Figure 13 is a simplified Block Diagram of the MSF transmit section.
2.7.4.1 TBUF
TBUF is a RAM that holds data and status to be transmitted. The data is written into sub-blocks
referred to as elements, by Microengines or the Intel XScale
® core.
TBUF contains a total of 8 Kbytes of data. The element size is programmable as either 64 bytes,
128 bytes, or 256 bytes per element. In addition, TBUF can be programmed to be split into one,
two, or three partitions depending on application. For transmitting SPI-4, one partition would be
used. For transmitting CSIX, two partitions are used (Control CFrames and Data CFrames). For
both SPI-4 and CSIX, three partitions are used.
Microengines can write data from Microengine S_TRANSFER_OUT registers to the TBUF using
the
msf[write]
instruction where they specify the starting byte number (which must be aligned to
4 bytes), and number of 32-bit words to write. The number in the instruction can be either the
number of 32-bit words, or number of 32-bit word pairs, using the single and double instruction
modifiers, respectively.
Microengines can move data from DRAM to TBUF using the
dram
instruction where they specify
the starting byte number (which must be aligned to 4 bytes), the number of 32-bit words to write,
and the address in DRAM of the data.
Figure 13. Simplified Transmit Section Block Diagram
A9366-01
RXCDAT
From Other CSRs
Internal Clock
for Transmit
Logic
From ME
From DRAM
TCLK
TCLK REF
RXCFC
(FCIFIFO full)
RXCSRB
(Ready Bits)
Internal
Clock
ME Reads
(S_Push_Bus)
Valid
Element
Logic
TDAT
TCTL
TPAR
FCIFIFO
- - - - - -
- - - - - -
- - - - - -
- - - - - -
TBUF
- - - - - -
- - - - - -
- - - - - -
- - - - - -
CSIX
Protocol
Logic
SPI-4
Protocol
Logic
Control
Byte Align