Intel NETWORK PROCESSOR IXP2800 - Manual (Page 139)

Hardware Reference Manual 139
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
Character Time-out Interrupt
When the receiver FIFO and receiver time-out interrupt are enabled, a character time-out interrupt
occurs when all of the following conditions exist:
• At least one character is in the FIFO.
• The last received character was longer than four continuous character times ago (if two stop
bits are programmed the second one is included in this time delay).
• The most recent processor read of the FIFO was longer than four continuous character times
ago.
The maximum time between a received character and a time-out interrupt is 160 ms at 300 baud
with a 12-bit receive character (i.e., 1 start, 8 data, 1 parity, and 2 stop bits).
When a time-out interrupt occurs, it is cleared and the timer is reset when the processor reads one
character from the receiver FIFO. If a time-out interrupt has not occurred, the time-out timer is
reset after a new character is received or after the processor reads the receiver FIFO.
Transmit Interrupt
When the transmitter FIFO and transmitter interrupt are enabled (UART_FCR[0]=1,
UART_IER[1]=1), transmit interrupts occur as follows:
• The Transmit Data Request interrupt occurs when the transmit FIFO is half empty or more
than half empty. The interrupt is cleared as soon as the Transmit Holding register is written
(1 to 64 characters may be written to the transmit FIFO while servicing the interrupt) or the IIR
is read.
3.12.3.1.2 FIFO Polled Mode Operation
With the FIFOs enabled (TRFIFOE bit of UART_FCR set to 1), setting UART_IER[4:0] to all 0s
puts the serial port in the FIFO polled mode of operation. Since the receiver and the transmitter are
controlled separately, either one or both can be in the polled mode of operation. In this mode,
software checks receiver and transmitter status via the UART_LSR. As stated in the register
description:
• UART_LSR[0] is set as long as there is one byte in the receiver FIFO.
• UART_LSR[1] through UART_LSR[4] specify which error(s) has occurred for the character
at the top of the FIFO. Character error status is handled the same way as interrupt mode. The
UART_IIR is not affected since UART_IER[2] = 0.
• UART_LSR[5] indicates when the transmitter FIFO needs data.
• UART_LSR[6] indicates that both the transmitter FIFO and shift register are empty.
• UART_LSR[7] indicates whether there are any errors in the receiver FIFO.
3.12.4 Baud Rate Generator
The baud rate generator is a programmable block and generates a clock used in the transmit block.
The output frequency of the baud rate generator is 16X the baud rate; baud rate is calculated as:
BaudRate = APB Clock / (16 X Divisor)
The Divisor ranges from 1 to 2 16 - 1. For example, for an APB clock of 1 MHz and a baud rate of
300 bps, the divisor is 209.