Intel NETWORK PROCESSOR IXP2800 - Manual (Page 304)

304 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
Information is passed across the interface in CFrames. CFrames are padded out to an integer
multiple of CWords. CFrames consist of a 2-byte base header, an optional 4-byte extension
header, a payload of 1 to 256 bytes, padding, and a 2-byte vertical parity. Transfers across the
interface are protected by a horizontal parity. When there is no information to pass over the
interface, an alternating sequence of Idle CFrames and Dead Cycles are passed across the interface.
There are 16 possible codes for CFrame types. Each CFrame type is either a data CFrame or a
control CFrame. Data CFrame types include Unicast, Multicast Mask, Multicast ID, Multicast
Binary Copy, and Broadcast. Control CFrames include Flow Control.
CSIX-L1 supports independent link-layer flow control for data CFrames and control CFrames by
using “ready bits” (CRdy and DRdy) in the base header. The response time for link-level flow
control is specified to be 32 interface clock ticks, but allows for additional time to complete
transmission of any CFrame already in progress at the end of that interval.
8.9.4.2 Intel
®
IXP2800 Support of the CSIX-L1 Protocol
The adaptation of the CSIX-L1 protocol to the network processor physical interface has been
accomplished in a straightforward manner.
8.9.4.2.1 Mapping to 16-Bit Wide DDR LVDS
The CSIX-L1 interface is built in units of 32 data bits. For each group of 32 data signals, there is a
clock signal (RxClk, TxClk), a start-of-frame signal (RxSOF, TxSOF) and a horizontal-parity
signal (RxPar, TxPar). If the CWord or interface width is greater than 32 bits, the assertion of the
Start-of-Frame signal associated with each group of 32 data bits is used to synchronize the transfers
across the independently clocked individual 32-bit interfaces.
The network processor supports 32-bit data transfers across two transfers or clock edges of the
SPI-4.2 16-bit DDR LVDS data interface. The CSIX-L1 RxSOF and TxSOF signals are mapped to
the SPI-4.2 TCTL and RCTL signals. For the transfer of CFrames, the start-of-frame signal is
asserted on only the first edge of the 32-bit transfer. (Assertion of the start-of-frame signal for
multiple contiguous clock edges denotes the start of a de-skew training sequence as described
below.)
Receiver logic for the interface should align the start of 32-bit transfers to the assertion of the start-
of-frame signal. The network processor always transmits the high order bits of a 32-bit transfer on
the rising edge of the transmit clock, but a receiver may de-skew the signals and align the received
data with the falling edge of the clock. The network processor receiver always aligns the received
data according to the assertion of the start-of-frame signal.
The network processor supports CWord widths of 32, 64, 96, and 128 bits. It will pad out CFrames
(including Idle CFrames) and Dead Cycles according to this CWord width. The physical interface
remains just 16 data bits. The start-of-frame signal is only asserted for the high order 16 bits of the
first 32-bit transfer; it is not asserted for each 32-bit transfer. Support for multiple CWord widths is
intended to facilitate implementation of IXP2800-to-CSIX-L1 translator chips and to facilitate
implementation of chips with native network processor interfaces, but with wider internal transfer
widths.
The network processor supports a horizontal parity signal (RPAR, TPAR). The horizontal parity
signal covers the 16 data bits that are transferred on each edge of the clock. It does not cover 32 bits
as in CSIX-L1. Support for horizontal-parity requires an additional physical signal beyond that
required for SPI-4.2. Checking of the horizontal parity can be optionally disabled on reception. If a
fabric interface chip does not support TPAR, then the checking of RPAR should be disabled.