Intel NETWORK PROCESSOR IXP2800 - Manual (Page 82)

82 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
3.3 Memory Management
The Intel XScale
®
core implements the Memory Management Unit (MMU) Architecture specified
in the ARM Architecture Reference Manual. To accelerate virtual to physical address translation,
the Intel XScale
®
core uses both an instruction Translation Look-aside Buffer (TLB) and a data
TLB to cache the latest translations. Each TLB holds 32 entries and is fully-associative. Not only
do the TLBs contain the translated addresses, but also the access rights for memory references.
If an instruction or data TLB miss occurs, a hardware translation-table-walking mechanism is
invoked to translate the virtual address to a physical address. Once translated, the physical address
is placed in the TLB along with the access rights and attributes of the page or section. These
translations can also be locked down in either TLB to guarantee the performance of critical
routines.
The Intel XScale ® core allows system software to associate various attributes with regions of
memory:
• cacheable
• bufferable
• line allocate policy
• write policy
• I/O
• mini Data Cache
• Coalescing
• P bit
Note: The virtual address with which the TLBs are accessed may be remapped by the PID register.
3.3.1 Architecture Model
3.3.1.1 Version 4 versus Version 5
ARM* MMU Version 5 Architecture introduces the support of tiny pages, which are 1 Kbyte in
size. The reserved field in the first-level descriptor (encoding 0b11) is used as the fine page table
base address.
3.3.1.2 Memory Attributes
The attributes associated with a particular region of memory are configured in the memory
management page table and control the behavior of accesses to the instruction cache, data cache,
mini-data cache and the write buffer. These attributes are ignored when the MMU is disabled.
To allow compatibility with older system software, the new Intel XScale ® core attributes take
advantage of encoding space in the descriptors that was formerly reserved.
3.3.1.2.1 Page (P) Attribute Bit
The P bit assigns a page attribute to a memory region. Refer to the Intel
®
IXP2400 and IXP2800
Network Processor Programmer’s Reference Manual for details about the P bit.