Intel NETWORK PROCESSOR IXP2800 - Manual (Page 283)

Hardware Reference Manual 283
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
The training sequence when the pins are used for SPI-4 Status Channel is shown in Table 109 .
This is compatible to SPI-4 training sequence.
8.6.3 Use of Dynamic Training
Dynamic training is done by cooperation of hardware and software as defined in this section.
The IXP2800 Network Processor will need training at reset or it loses training. Loss of training will
typically be detected by parity errors on received data. Table 110 lists the steps to initiate the
training. SPI-4, CSIX Full Duplex, and CSIX Simplex cases follow similar but slightly different
sequences. The SPI-4 protocol uses the calendar status pins, TSTAT/RSTAT (or RXCDAT/
TXCDAT if those are used for calendar status), as an indicator that data training is required. For
CSIX use, the IXP2800 Network Processor uses a proprietary method of in-band signaling using
Idle CFrames and Dead Cycles to indicate the need for training.
Until the LVDS IOs are deskewed correctly, DIP-4 errors will occur. At startup, the receiver should
request training followed by the transmitting device being sent training. The receiver should
initially see received_training set and DIP-4 parity errors. The receiver should then clear the parity
errors, wait for receive_training set and dip4_error cleared and check that all of the applicable
RX_PHASEMON registers indicate no training errors . Then the LVDS IOs are properly trained.
Table 109. Calendar Training Sequence
Cycle
(Note 3)
XCDAT
1 0
1 to 10 0 0
11 to 20 1 1
20 α -19 to 20 α -10 0 0
20 α -9 to 20 α 1 1
NOTE:
1. α represents the number of repeats, as specified in SPI-4 specification. When the IXP2800 Network
Processor is transmitting training sequences the value is in Train_Calendar[Alpha].
2. On receive, the IXP2800 Network Processor will do dynamic deskew when
Train_Calendar[Ignore_Training] is 0, and TCDAT= 0x0 for ten consecutive samples.
3. These are really phases (i.e.,each edge of the clock is counted as one sample).
4. Only XCDAT[1:0] are included in training.