Intel NETWORK PROCESSOR IXP2800 - Manual (Page 197)

Hardware Reference Manual 197
Intel
®
IXP2800 Network Processor
DRAM
5.8 Microengine Signals
Upon completion of a read or write, the RDRAM controller can signal a Microengine context,
when enabled. It does so using the
sig_done
token; see Example 27 .
Because the RDRAM address space is interleaved, consecutive accesses can go to different
RDRAM channels. There is no ordering guaranteed among different channels, so a separate signal
is needed for each.
In addition, because accesses start at any address, and can specify up to 16 64-bit words
(128 bytes), they can also split across two channels (refer to
Section 5.5 ). The ctx_arb instruction
must set two Wakeup_Events (an odd/even pair) per access. The RDRAM controllers coordinate as
follows:
• If the access split across two channels, the channel handling the low part of the split delivers
the even-numbered Event Signal, and the channel handling the upper part of the split delivers
the odd-numbered Event Signal.
• If the access does not split, the channel delivers both Event Signals (by coordinating with the
D_Push or D_Pull arbiter for read and writes respectively).
• In all cases, the channel delivers the Event Signal with the last data Push or Pull of a burst.
Using the above rules, the Microengine will be put into the Ready State (ready to resume
executing) only when all accesses have completed.
5.9 Serial Port
The RDRAM chips are configured through a serial port, which consists of signals D_SIO,
D_CMD, and D_SCK. Access to the serial port is via the RDRAM_Serial_Command and
RDRAM_Serial_Data CSRs (refer to the IXP2400 and IXP2800 Network Processor Programmer’s
Reference Manual for the register descriptions).
All serial commands are initiated by a write to RDRAM_Serial_Command. Because the serial port
is slow, RDRAM_Serial_Command has a Busy bit, which indicates that a serial port command is
in progress. Software must test this bit before initiating a command. This ensures that software will
not lose a command, while eliminating the need for a hardware FIFO for serial commands.
Serial writes are done by the following steps:
1. Read RDRAM_Serial_Command; test Busy bit until its a 0.
2. Write RDRAM_Serial_Data.
3. Write RDRAM_Serial_Command to start the write.
Example 27. RDRAM Controller Signaling a Microengine Context
dram [read,$xfer6,addr_a,0,1], sig_done_4
dram [read,$xfer7,addr_b,0,1], sig_done_6
ctx_arb[4, 5, 6, 7]