2 branch instruction timings, 3 data processing instruction timings, Branch instruction timings – Intel NETWORK PROCESSOR IXP2800 User Manual
Page 115: Data processing instruction timings
Hardware Reference Manual
115
Intel
®
IXP2800 Network Processor
Intel XScale
®
Core
3.9.4.2
Branch Instruction Timings
(
3.9.4.3
Data Processing Instruction Timings
Table 28. Branch Instruction Timings (Predicted by the BTB)
Mnemonic
Minimum Issue Latency when Correctly
Predicted by the BTB
Minimum Issue Latency with Branch
Misprediction
B
1
5
BL
1
5
Table 29. Branch Instruction Timings (Not Predicted by the BTB)
Mnemonic
Minimum Issue Latency when
the branch is not taken
Minimum Issue Latency when
the branch is taken
BLX(1)
N/A
5
BLX(2)
1
5
BX
1
5
Data Processing Instruction with
PC as the destination
Same as
4 + numbers in
LDR PC,<>
2
8
LDM with PC in register list
3 + numreg
1
1.
numreg is the number of registers in the register list including the PC.
10 + max (0, numreg-3)
Table 30. Data Processing Instruction Timings
Mnemonic
<shifter operand> is not a Shift/Rotate
by Register
<shifter operand> is a Shift/Rotate by
Register or
<shifter operand> is RRX
Minimum Issue
Latency
Minimum Result
Latency
1
1.
If the next instruction needs to use the result of the data processing for a shift by immediate or as Rn in a QDADD or QDSUB,
one extra cycle of result latency is added to the number listed.
Minimum Issue
Latency
Minimum Result
Latency
ADC
1
1
2
2
ADD
1
1
2
2
AND
1
1
2
2
BIC
1
1
2
2
CMN
1
1
2
2
CMP
1
1
2
2
EOR
1
1
2
2
MOV
1
1
2
2
MVN
1
1
2
2
ORR
1
1
2
2
RSB
1
1
2
2
RSC
1
1
2
2
SBC
1
1
2
2
SUB
1
1
2
2
TEQ
1
1
2
2
TST
1
1
2
2