Intel NETWORK PROCESSOR IXP2800 - Manual (Page 155)

Hardware Reference Manual 155
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
3.12.7.7.2 Mode 2: Interface with 8 Data Bits and 11 Address Bits
This application is designed for the PMC-Sierra* PM5351 S/UNI-TETRA* device. For the
PMC-Sierra* PM5351, the address space is programmed to 11 bits; otherwise, other address space
should be specified.
8-Bit PMC-Sierra* PM5351 S/UNI-TETRA* Interfacing Topology
Figure 45 displays one of the topologies used to connect to the Slowport with the PMC-Sierra*
PM5351 S/UNI-TETRA* device.
From Figure 45 , because the protocols are very close to the generic Slowport protocol, the pin
counts and the functionality is quite compatible. We do not need to use any more pins in this case.
The only difference is in the INTB signal, which will be connected to the SP_ACK_L. Therefore,
the SP_ACK_L needs to be converted to an interrupt signal.
Also because the address contains only 11bits, two 74F377 or equivalent buffers are needed.
The AS field in the SP_ADC register should be programmed to a 16-bit addressing space with the
upper five address bits unconnected.
The timing controls are similar to the generic case.
Figure 45. An Interface Topology with PMC-Sierra* PM5351 S/UNI-TETRA*
A9369-04
SP_RD_L
SP_CS_L[1]
SP_ACK_L
SP_AD[7:0]
CE#
CP
D[7:0]
Q[7:0]
74F377
SP_WR_L
RDB
ALE
CSB
INTB
WRB
DATA[7:0]
ADDR[10:0]
Intel ® IXP2800
Network
Processor
PMC-Sierra*
PM5351
SP_ALE_L
SP_CLK
CE#
CP
D[7:0]
ADDR[10:8]
ADDR[7:0]
VCC
Q[7:0]
74F377
Clock
Driver
CY2305