48 byte-enable generation by the, Figure 25 – Intel NETWORK PROCESSOR IXP2800 User Manual

Page 124

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124

Hardware Reference Manual

Intel

®

IXP2800 Network Processor

Intel XScale

®

Core

Word Write (16-Bits Write)

When the Intel XScale

®

core writes a 16-bit word to external memory, it puts the bytes in the byte

lanes where it intends to write them along with the byte enables for those bytes turned ON based on

the endian setting of the system. The Intel XScale

®

core does not allow a word write on an

odd-byte address. The Intel XScale

®

core register bits [15:0] always contain the word to be written

regardless of the B-bit setting.

For example, if the Intel XScale

®

core wants to write one word to a little-endian system at address

0x0002, it will copy byte 0 to byte lane 2 and byte 1 to byte lane 3 along with X_BE[2] and

X_BE[3] turned ON. If the Intel XScale

®

core wants to write one word to a big-endian system at

address 0x0002, it will copy byte 0 to byte lane 0 and byte 1 to byte lane 1 along with X_BE[0] and

X_BE[1] turned ON.

Table 48

shows other possible combinations of byte lanes and byte enables.

Byte lanes other than those currently driven by the Intel XScale

®

core contain undefined data.

Longword (32-Bits) Write

The longword to be written is put on the Intel XScale

®

core’s data bus with byte 0 on X[7:0],

byte 1 on X[15:8], byte 2 on X[23:16], and byte 4 on X[31:24] (see

Figure 25

). All of the byte

enables are turned ON. A 32-bit longword write (0x12345678) by the Intel XScale

®

core to address

0x0000 regardless of endianness, causes byte 0 (0x78) to be written to address 0x0000, byte 1
(0x56) to address 0x0001, byte 2 (0x34) to address 0x0002, and byte 3 (0x12) to address 0x0003.

Table 48. Byte-Enable Generation by the Intel XScale

®

Core for Word Writes in Little- and

Big-Endian Systems

Word

to be

Written

Byte-Enables for Little-Endian Systems

Byte-Enables for Big-Endian Systems

X_BE[0]

X_BE[1]

X_BE[2]

X_BE[3]

X_BE[0]

X_BE[1]

X_BE[2]

X_BE[3]

Byte 0,
Byte 1

1

1

0

0

0

0

1

1

Byte 2,
Byte 3

0

0

1

1

1

1

0

0

Figure 25. Intel XScale

®

Core-Initiated Write to the IXP2800 Network Processor

A9695-03

Byte

Write

M[7:0]

M[15:8]

M[23:16]

M[31:24]

X [7:0]

X_BE [0]

X [15:8]

X [23:18]

X [31:24]

Byte Write by Intel XScale

®

Core

Intel

®

IXP2800

Core Gasket

X_BE [1]

X_BE [2]

X_BE [3]

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