Intel NETWORK PROCESSOR IXP2800 - Manual (Page 20)

20 Hardware Reference Manual
Contents
47 Byte-Enable Generation by the Intel XScale ® Core for Byte Writes in Little- and
Big-Endian Systems ................................................................................................................. 123
48 Byte-Enable Generation by the Intel XScale ® Core for Word Writes in Little- and
Big-Endian Systems ................................................................................................................. 124
49 CMB Write Command to CPP Command Conversion ............................................................. 127
50 IXP2800 Network Processor SRAM Q-Array Access Alias Addresses .................................... 129
51 GCSR Address Map (0xd700 0000)......................................................................................... 131
52 Data Transaction Alignment ..................................................................................................... 136
53 Address Spaces for XPI Internal Devices................................................................................. 136
54 8-Bit Flash Memory Device Density ......................................................................................... 143
55 SONET/SDH Devices............................................................................................................... 143
56 Next Neighbor Write as a Function of CTX_Enable[NN_Mode] ............................................... 172
57 Registers Used by Contexts in Context-Relative Addressing Mode......................................... 173
58 Align Value and Shift Amount................................................................................................... 174
59 Register Contents for Example 23............................................................................................ 175
60 Register Contents for Example 24............................................................................................ 176
61 RDRAM Loading....................................................................................................................... 188
62 RDRAM Sizes........................................................................................................................... 188
63 Address Rearrangement for 3-Way Interleave (Sheet 1 of 2) .................................................. 192
64 Address Rearrangement for 3-Way Interleave (Sheet 2 of 2) (Rev B) .................................... 193
65 Address Bank Interleaving........................................................................................................ 194
66 RDRAM Timing Parameter Settings......................................................................................... 196
67 Ordering of Reads and Writes to the Same Address for DRAM............................................... 201
68 DRAM Push Arbiter Operation ................................................................................................. 203
69 DPLA Description ..................................................................................................................... 204
70 SRAM Controller Configurations .............................................................................................. 209
71 Total Memory per Channel ....................................................................................................... 210
72 Atomic Operations .................................................................................................................... 212
73 Queue Format .......................................................................................................................... 215
74 Ring/Journal Format ................................................................................................................. 216
75 Ring Size Encoding .................................................................................................................. 216
76 Address Map ............................................................................................................................ 218
77 Address Reference Order......................................................................................................... 219
78 Q_array Entry Reference Order ............................................................................................... 220
79 Ring Full Signal Use – Number of Contexts and Length versus Ring Size .............................. 232
80 Head/Tail, Base, and Full Threshold – by Ring Size ................................................................ 233
81 Intel XScale® Core and Microengine Instructions .................................................................... 235
82 S_Transfer Registers Hash Operands ..................................................................................... 237
83 SPI-4 Control Word Format ...................................................................................................... 244
84 Order of Bytes within the SPI-4 Data Burst .............................................................................. 245
85 CFrame Types.......................................................................................................................... 246
86 Receive Pins Usage by Protocol .............................................................................................. 248
87 Order in which Received Data Is Stored in RBUF.................................................................... 248
88 Mapping of Received Data to RBUF Partitions ........................................................................ 249
89 Number of Elements per RBUF Partition.................................................................................. 249
90 RBUF SPIF-4 Status Definition ................................................................................................ 252
91 RBUF CSIX Status Definition ................................................................................................... 254
92 Rx_Thread_Freelist Use........................................................................................................... 255
93 Summary of SPI-4 and CSIX RBUF Operations ...................................................................... 258
94 Transmit Pins Usage by Protocol ............................................................................................. 262