Intel NETWORK PROCESSOR IXP2800 - Manual (Page 33)

Hardware Reference Manual 33
Intel
®
IXP2800 Network Processor
Technical Description
2.3 Microengines
The Microengines do most of the programmable pre-packet processing in the IXP2800 Network
Processor. There are 16 Microengines, connected as shown in Figure 1 . The Microengines have
access to all shared resources (SRAM, DRAM, MSF, etc.) as well as private connections between
adjacent Microengines (referred to as “next neighbors”).
The block diagram in Figure 4 is used in the Microengine description. Note that this block diagram
is simplified for clarity; some blocks and connectivity have been omitted to make the diagram
more readable. Also, this block diagram does not show any pipeline stages, rather it shows the
logical flow of information.
Microengines provide support for software-controlled multi-threaded operation. Given the
disparity in processor cycle times versus external memory times, a single thread of execution often
blocks, waiting for external memory operations to complete. Multiple threads allow for thread-
interleave operation, as there is often at least one thread ready to run while others are blocked.