Intel NETWORK PROCESSOR IXP2800 - Manual (Page 375)

Hardware Reference Manual 375
Intel
®
IXP2800 Network Processor
Performance Monitor Unit
Performance Monitor Unit
11
11.1 Introduction
The Performance Monitor Unit (PMU) is a hardware block consisting of counters and comparators
that can be programmed and controlled by using a set of configured registers to monitor and to fine
tune performance of different hardware units in the IXP2800 Network Processor. The total number
of such counters needed is determined based on the different events and functions that must be
monitored concurrently. Observation of such events on the chip is used for statistical analysis,
uncovering bottlenecks, and to tune the software to fit the hardware resources.
11.1.1 Motivation for Performance Monitors
For a given set of functionality, a measure of performance is very important in making decisions on
feature sets to be supported, and to tune the embedded software on the chip. An accurate estimate
of latency and speed in hardware blocks enables firmware and software designers to understand the
limitations of the chip and to make prudent judgments about its software architecture. The current
generation does not provide any performance monitor hooks.
Since IXP2800 Network Processors are targeted for high performance segments (OC-48 and
above), the need for tuning the software to get the most out of the hardware resources becomes
extremely critical. The performance monitors provide valuable insight into the chip by providing
real-time data on latency and utilization of various resources. See Figure 136 for the Performance
Monitor Interface Block Diagram.