Intel NETWORK PROCESSOR IXP2800 - Manual (Page 97)

Hardware Reference Manual 97
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
3.6.1 Overviews
3.6.1.1 Data Cache Overview
The data cache is a 32-Kbyte, 32-way set associative cache, i.e., there are 32 sets and each set has
32 ways. Each way of a set contains 32 bytes (one cache line) and one valid bit. There also exist
two dirty bits for every line, one for the lower 16 bytes and the other one for the upper 16 bytes.
When a store hits the cache, the dirty bit associated with it is set. The replacement policy is a
round-robin algorithm and the cache also supports the ability to reconfigure each line as data RAM.
Figure 22 shows the cache organization and how the data address is used to access the cache.
Cache policies may be adjusted for particular regions of memory by altering page attribute bits in
the MMU descriptor that controls that memory.
The data cache is virtually addressed and virtually tagged. It supports write-back and write-through
caching policies. The data cache always allocates a line in the cache when a cacheable read miss
occurs and will allocate a line into the cache on a cacheable write miss when write allocate is
specified by its page attribute. Page attribute bits determine whether a line gets allocated into the
data cache or mini-data cache.
Figure 22. Data Cache Organization
A9689-01
32 bytes (cache line)
Data CAM
Tag
Data Address (Virtual)
Note: CAM = Content Addressable Memory
Set Index
Word Select
Byte Alignment
Sign Extension
Data Word
(4 bytes to Destination Register)
Word Byte
way 0
Set 31
Set 1
way 1
31 5 4 2 1 0 10 9
32 bytes (cache line)
Data CAM
way 0
way 1
Set 0
32 bytes (cache line)
Data CAM
way 0
way 1
way 31
Byte Select
Tag
This example
shows Set 0 being
selected by the
Set Index
Set Index