Intel NETWORK PROCESSOR IXP2800 - Manual (Page 234)

234 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
SHaC — Unit Expansion
For writes using the Reflector mode, Scratchpad arbitrates for the S_Pull_Bus, pulls the write data
from the source identified in the instruction (either a Microengine transfer register or an Intel
XScale
®
core write buffer), and puts it into one of the Pull Data FIFOs (same as for APB and CAP
CSR writes). The data is then removed from the Pull Data FIFO and sent to the Push Arbiter.
For CSR Fast Writes, the command bypasses the Inlet Command FIFO and is acted on at first
opportunity. The CSR control logic has an arbiter that gives highest priority to fast writes. If an
APB write is in progress when a fast write arrives, both write operations will complete
simultaneously. For a CSR fast write, the Scratchpad extracts the write data from the command,
instead of pulling the data from a source over the Pull bus. It then drives the address and writes data
to all CSRs on the CAP CSR bus, using the same method used for the CAP CSR write.
The Scratchpad unit supports CAP write operations with burst counts greater than 1, except for fast
writes, which only support a burst count of 1. Burst support is required primarily for Reflector
mode and software must ensure that burst is performed to a non-contiguous set of registers. CAP
looks at the length field on the command bus and breaks each count into a separate APB write
cycle, incrementing the CSR number for each bus access.
Reads
For an APB read, the Scratchpad drives the address, write, select, and enable signals, and then
waits for the acknowledge signal (APB_RDY_H) from the APB device. For a CAP CSR read, the
address is driven, which controls a tree of multiplexers to select the appropriate CSR. CAP then
waits for the acknowledge signal (CAP_CSR_RD_RDY).
Note: The CSR bus can support an acknowledge signal since the read operations occur on a separate read
bus and will not interfere with Fast Write operations. In both cases, when the data is returned, the
data is sent to the Push Arbiter and the Push Arbiter pushes the data to the destination.
For reads using the Reflector mode, the write data is pulled from the source identified in
ADDRESS (either a Microengine transfer register or an Intel XScale ® core write buffer), and put
into one of the Scratchpad Pull Data FIFOs. The data is then sent to the Push Arbiter. The arbiter
then moves the data to the destination specified in the command. Note that this is the same as a
Reflector mode write, except that the source and destination are identified using opposite fields.
The Scratchpad performs one read operation at a time. In other words, CAP does not begin an APB
read until a CSR read has completed, or vice versa. This simplifies the design by ensuring that,
when lengths are greater than 1, the data is sent to the Push Arbiter in a contiguous order and not
interleaved with data from a read on the other bus.
Signal Done
CAP can provide a signal to a Microengine upon completion of a command. For APB and CAP
CSR operations, CAP signals the Microengine using the same method as any other target. For
Reflector mode reads and writes, CAP uses the TOKEN field of the Command to determine
whether to signal the command initiator, the Microengine that is the target of the reflection, both, or
neither.