Intel NETWORK PROCESSOR IXP2800 - Manual (Page 272)

272 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Media and Switch Fabric Interface
The TX_Port_Status_# or the TX_Multiple_Port_Status_# registers must be read by the
software to determine the status of each port and send data to them accordingly. The MSF hardware
does not check these registers for port status before sending data out to a particular port.
The MSF_Tx_Control[Tx_Status_Update_Mode] field is used to select one of two methods for
updating the port status. The first method updates the port status with the new status value,
regardless of the value received. The second method updates the port status only when a value is
received that is equal to or less than the current value.
Note: Detailed information about the status update modes is contained in the Intel ® IXP2400 and
IXP2800 Network Processor Programmer’s Reference Manual.
Reading a port status causes its value to be changed. This provides a way to avoid reading stale
status bits. The MSF_Tx_Control[Tx_Status_Read_Mode] field is used to select the method for
changing the bits after they are read.
Tx_Calendar is a RAM with 256 entries of eight bits each. It is initialized with the calendar
information by software (the calendar is a list that indicates the sequence of port status that will be
sent — the PHY and the IXP2800 Network Processor must be initialized with the same calendar).
Tx_Calendar_Length is a CSR field that is initialized with the length of the calendar, since in
many cases, not all 256 entries of Tx_Calendar are used.
When the start of a Status frame pattern is detected (by a value of 0x3 on TSTAT) the Calendar
Counter is initialized to 0. On each data cycle, the Calendar Counter is used to index into
Tx_Calendar to read a port number. The port number is used as an index to Tx_Port_Status, and
the information received on TSTAT is put into that location in Tx_Port_Status. The count is
incremented each cycle.
DIP-2 Parity is also accumulated on TSTAT. At the start of the frame, parity is cleared. When the
count reaches Tx_Calendar_Length, the next value on TSTAT is used to compare to the
accumulated parity. The control logic then looks for the next frame start. If the received parity does
not match the expected value, the MSF_Interrupt_Status[TSTAT_Par_Err] bit is set, which can
interrupt the Intel XScale ® core if enabled.
Note: An internal status flag records whether or not the most recently received DIP-2 was correct. When
that flag is set (indicating bad DIP-2 parity) all reads to Tx_Port_Status return a status of
“Satisfied” instead of the value in the Tx_Port_Status RAM. The flag is re-loaded at the next
parity sample; so the implication is that all ports will return “Satisfied” status for at least one
calendar.
SPI-4 protocol uses a continuous stream of repeated frame patterns to indicate a disabled status
link. The IXP2800 Network Processor flow control status block has a Frame Pattern Counter that
counts up each time a frame pattern is received on TSTAT, and is cleared when any other pattern is
received. When the Frame Pattern Counter reaches 32,
MSF_Interrupt_Status[Detect_No_Calendar] is set and Train_Data[Detect_No_Calendar] is
asserted (MSF_Interrupt_Status[Detect_No_Calendar] must be cleared by a write to the
MSF_Interrupt_Status register; Train_Data[Detect_No_Calendar] will reflect the current
status and will deassert when the frame pattern stops). The transmit logic will generate training
sequence on transmit pins while both Train_Data[Detect_No_Calendar] and
Train_Data[Train_Enable_TSTAT] are asserted.