Intel NETWORK PROCESSOR IXP2800 - Manual (Page 25)

Hardware Reference Manual 25
Intel
®
IXP2800 Network Processor
Introduction
Introduction
1
1.1 About This Document
This document is the hardware reference manual for the Intel ® IXP2800 Network Processor.
This information is intended for use by developers and is organized as follows:
Section 2, “Technical Description” contains a hardware overview.
Section 3, “Intel XScale
®
Core” describes the embedded core.
Section 4, “Microengines” describes Microengine operation.
Section 5, “DRAM” describes the DRAM Unit.
Section 6, “SRAM Interface” describes the SRAM Unit.
Section 7, “SHaC — Unit Expansion” describes the Scratchpad, Hash Unit, and CSRs (SHaC).
Section 8, “Media and Switch Fabric Interface” describes the Media and Switch Fabric (MSF)
Interface used to connect the network processor to a physical layer device.
Section 9, “PCI Unit” describes the PCI Unit.
Section 10, “Clocks and Reset” describes the clocks, reset and initialization sequence.
Section 11, “Performance Monitor Unit” describes the PMU.
1.2 Related Documentation
Further information on the IXP2800 is available in the following documents:
IXP2800 Network Processor Datasheet – Contains summary information on the IXP2800 Network
Processor including a functional description, signal descriptions, electrical specifications, and
mechanical specifications.
IXP2400 and IXP2800 Network Processor Programmer’s Reference Manual – Contains detailed
programming information for designers.
IXP2400/IXP2800 Network Processor Development Tools User’s Guide – Describes the Developer
Workbench and the development tools you can access through the use of the Workbench GUI.