Intel NETWORK PROCESSOR IXP2800 - Manual (Page 356)

356 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
PCI Unit
Table 141. Byte Enable Alignment for 32-Bit PCI Data In (32 Bits PCI Big-Endian to Big-Endian
without Swap)
PCI Add[2]=1 PCI Add[2]=0
Longword1byte enable
LW1 byte enable drive after LW0 byte enable
Longword0 byte enable
LW0 byte enable drive first
PCI Data IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
SRAM Data
OUT_BE[0] OUT_BE[1] OUT_BE[2] OUT_BE[3] OUT_BE[0] OUT_BE[1] OUT_BE[2] OUT_BE[3]
Longword1byte enable
LW1 byte enable drive after LW0 byte enable
Longword0 byte enable
LW0 byte enable drive first
direct map
pci to dram
IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
DRAM Data OUT_BE[4] OUT_BE[5] OUT_BE[6] OUT_BE[7] OUT_BE[0] OUT_BE[1] OUT_BE[2] OUT_BE[3]
Table 142. Byte Enable Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Little
Endian with Swap)
SRAM Data
IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
Longword1byte enable
LW1 byte enable drive after LW0 byte enable
Longword0 byte enable
LW0 byte enable drive first
DRAM Data IN_BE[4] IN_BE[5] IN_BE[6] IN_BE[7] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
PCI Side OUT_BE[7] OUT_BE[6] OUT_BE[5] OUT_BE[4] OUT_BE[3] OUT_BE[2] OUT_BE[1] OUT_BE[0]
Table 143. Byte Enable Alignment for 64-Bit PCI Data Out (Big-Endian to 64 Bits PCI Big
Endian without Swap)
SRAM Data IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
Longword1byte enable
LW1 byte enable drive after LW0 byte enable
Longword0 byte enable
LW0 byte enable drive first
DRAM Data IN_BE[4] IN_BE[5] IN_BE[6] IN_BE[7] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
PCI Side OUT_BE[4] OUT_BE[5] OUT_BE[6] OUT_BE[7] OUT_BE[0] OUT_BE[1] OUT_BE[2] OUT_BE[3]
Table 144. Byte Enable Alignment for 32-Bit PCI Data Out (Big-Endian to 32 Bits PCI Little
Endian with Swap)
SRAM Data IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
Longword1byte enable
LW1 byte enable drive after LW0 byte enable
Longword0 byte enable
LW0 byte enable drive first
DRAM Data IN_BE[4] IN_BE[5] IN_BE[6] IN_BE[7] IN_BE[0] IN_BE[1] IN_BE[2] IN_BE[3]
PCI Data OUT_BE[3] OUT_BE[2] OUT_BE[1] OUT_BE[0] OUT_BE[3] OUT_BE[2] OUT_BE[1] OUT_BE[0]
Longword1byte enable
LW1 byte enable drive after LW0 byte enable
Longword0 byte enable
LW0 byte enable drive first
PCI Add[2]=1 PCI Add[2]=0