Intel NETWORK PROCESSOR IXP2800 - Manual (Page 30)

30 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Technical Description
2.2 Intel XScale
®
Core Microarchitecture
The Intel XScale
®
microarchitecture consists of a 32-bit general purpose RISC processor that
incorporates an extensive list of architecture features that allows it to achieve high performance.
2.2.1 ARM* Compatibility
The Intel XScale
®
microarchitecture is ARM* Version 5 (V5) Architecture compliant. It
implements the integer instruction set of ARM* V5, but does not provide hardware support of the
floating point instructions.
The Intel XScale
®
microarchitecture provides the Thumb instruction set (ARM V5T) and the
ARM V5E DSP extensions.
Backward compatibility with the first generation of StrongARM* products is maintained for user-
mode applications. Operating systems may require modifications to match the specific hardware
features of the Intel XScale
®
microarchitecture and to take advantage of the performance
enhancements added to the Intel XScale
®
core.
2.2.2 Features
2.2.2.1 Multiply/Accumulate (MAC)
The MAC unit supports early termination of multiplies/accumulates in two cycles and can sustain a
throughput of a MAC operation every cycle. Several architectural enhancements were made to the
MAC to support audio coding algorithms, which include a 40-bit accumulator and support for
16-bit packed values.
2.2.2.2 Memory Management
The Intel XScale ® microarchitecture implements the Memory Management Unit (MMU)
Architecture specified in the ARM Architecture Reference Manual. The MMU provides access
protection and virtual to physical address translation.
The MMU Architecture also specifies the caching policies for the instruction cache and data
memory. These policies are specified as page attributes and include:
• identifying code as cacheable or non-cacheable
• selecting between the mini-data cache or data cache
• write-back or write-through data caching
• enabling data write allocation policy
• and enabling the write buffer to coalesce stores to external memory
2.2.2.3 Instruction Cache
The Intel XScale
®
microarchitecture implements a 32-Kbyte, 32-way set associative instruction
cache with a line size of 32 bytes. All requests that “miss” the instruction cache generate a 32-byte
read request to external memory. A mechanism to lock critical code within the cache is also
provided.