Intel NETWORK PROCESSOR IXP2800 - Manual (Page 86)

86 Hardware Reference Manual
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
3.3.4.3 Locking Entries
Individual entries can be locked into the instruction and data TLBs. If a lock operation finds the
virtual address translation already resident in the TLB, the results are unpredictable. An invalidate
by entry command before the lock command will ensure proper operation. Software can also
accomplish this by invalidating all entries, as shown in
Example 15 .
Locking entries into either the instruction TLB or data TLB reduces the available number of entries
(by the number that was locked down) for hardware to cache other virtual to physical address
translations.
A procedure for locking entries into the instruction TLB is shown in Example 15 .
If a MMU abort is generated during an instruction or data TLB lock operation, the Fault Status
register is updated to indicate a Lock Abort, and the exception is reported as a data abort.
Note: If exceptions are allowed to occur in the middle of this routine, the TLB may end up caching a
translation that is about to be locked. For example, if R1 is the virtual address of an interrupt
service routine and that interrupt occurs immediately after the TLB has been invalidated, the lock
operation will be ignored when the interrupt service routine returns back to this code sequence.
Software should disable interrupts (FIQ or IRQ) in this case.
As a general rule, software should avoid locking in all other exception types.
Example 15. Locking Entries into the Instruction TLB
; R1, R2 and R3 contain the virtual addresses to translate and lock into
; the instruction TLB.
; The value in R0 is ignored in the following instruction.
; Hardware guarantees that accesses to CP15 occur in program order
MCR P15,0,R0,C8,C5,0 ; Invalidate the entire instruction TLB
MCR P15,0,R1,C10,C4,0 ; Translate virtual address (R1) and lock into
; instruction TLB
MCR P15,0,R2,C10,C4,0 ; Translate
; virtual address (R2) and lock into instruction TLB
MCR P15,0,R3,C10,C4,0 ; Translate virtual address (R3) and lock into
; instruction TLB
CPWAIT
; The MMU is guaranteed to be updated at this point; the next instruction will
; see the locked instruction TLB entries.