Intel NETWORK PROCESSOR IXP2800 - Manual (Page 157)

Hardware Reference Manual 157
Intel
®
IXP2800 Network Processor
Intel XScale ® Core
Figure 47 , depicts a single read transaction launched from the IXP2800 Network Processor to the
PMC-Sierra* PM5351 device, followed by a single write transaction.
In this case, there are ten clock cycles of access time, or 200 ns in total, with three turnaround
cycles attached at the back. The I/O throughput is 11.2 Mbytes per second.
3.12.7.7.3 Mode 3: Support for the Intel and AMCC* 2488 Mbps
SONET/SDH Microprocessor Interface
The user has to configure the address bus to 10 bits.
Mode 3 Interfacing Topology
Figure 48 demonstrates one of the topologies used to connect the Slowport to the Intel and AMCC*
2488-Mbps SONET/SDH device. Similar to the Lucent* TDAT042G5 interface, the address and
the data need demultiplexing. Totally, it requires four buffers to accomplish this task.
The SP_RD_L, SP_WR_L, and SP_CS_L[1] entirely match the RDB, WRB, and CSB pins in the
Intel and AMCC* component. However, the INT has to be connected to the SP_ACK_L as the
PMC-Sierra* Interface does. The ALE pin shares the SP_CP signal. If the timing does not meet
specification, then ALE can be tied high as shown in Figure 49 . It employs the same method as
Lucent*’s TDAT042G5’s topology to pack and unpack the data between the IXP2800 Slowport
interface and the Intel and AMCC* microprocessor interface.
Figure 47. Mode 2 Single Read Transfer for PMC-Sierra* PM5351 Device (B0)
B1748-03
SP_CLK
SP_ALE_L
SP_CS_L[1]/CSB
SP_WR_L/WRB
SP_RD_L/RDB
2 0 4 6 8 10 12 14 16 18 20 22 24
SP_AD[7:0]
SP_ACK_L/INTB
SP_CP
SP_OE_L
A[10:0]
SP_DIR
ADDR[15:0]
DATA[7:0]
A
[15:8]
A
[10:8]
A
[7:0] D[7:0]
D[7:0] A
[10:8]
A
[7:0]
A
[10:8]
A
[7:0]
A
[10:8]
A
[7:0] D[7:0]
A
[10:0]
A
[10:0]
A
[7:0]
A
[10:8]
A
[7:0]
D[7:0] A
[10:8]
A
[7:0]
A
[10:8]
A
[7:0]
A[10:0]