Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 100)

7–18 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
Figure 7–10. SMA DPA Top-Level BDF
The system clock is generated by an enhanced PLL using the on-board
33.33-MHz crystal oscillator as the reference clock. The PLL generates a
125-MHz clock that clocks the data generation logic and serves as the
reference for the LVDS transmitter on the Stratix GX device.
The transmit PRBS generator is constructed with eight 5-bit linear
feedback shift registers. The output is taken from the MSB of each shift
register. The initial seed value is 8’h47. When the enable (start) signal is
high, the generator outputs a 31-word sequence that repeats until
stopped. On reset, the seed value is initialized into all of the registers. This
generator generates the data stream that exercises the system. Each
transmit channel has its own PRBS generator.
The DPA technology requires a training pattern to be sent prior to the
start of data transmission. An 8-bit counter and a fixed pattern generator
create the training pattern. When you press the start button, the counter
starts and the fixed pattern is transmitted. When the counter reaches 256,
a start signal is sent to the PRBS generator and the output multiplexer
switches over to the PRBS data.