Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 93)

Altera Corporation Quartus II Version 3.0 7–11
Diagnostic Test Details Standard Tests
Each transmit channel has its own PRBS generator that comprises eight
5-bit linear feedback shift registers. The output is taken from the MSB of
each shift register. The initial seed value is 8’h47. When the enable (start)
signal is high, the generator outputs a 31-word sequence that repeats
until stopped. On reset, the seed value is initialized into all of the
registers. This generator creates the data stream that exercises the system.
The edge generator uses channel 0 to transmit a signal to the receive
channel that data is being transmitted. When stopped, the output is 8’h00.
When running, the output is 8’hFF. This signal is synchronized with the
start of the PRBS generator.
The data from the PRBS generators and the edge generator is combined
and sent to an LVDS transmit megafunction created using the Altera
MegaWizard Plug-In Manager. The megafunction is configured with 16
channels running at 840 Mbps and a clock rate of 105 MHz. The signals
are sent to the Stratix device as 16 serial data channels at 840 Mbps with
a clock signal of 105 MHz.
The Stratix device receives the signals and converts them back into
parallel data using an LVDS receive megafunction (128 bits at 105 MHz).
The parallel data is sent to an LVDS transmitter and sent back to the
Stratix GX device as serial data. An LVDS receive megafunction on the
Stratix GX device converts the serial data back to parallel and generates
the clock used to regulate the receive channel logic.
The edge detector monitors channel 0 for 1s. Depending on when the 1s
appear in the 8-bit data word, it generates a shift value to realign the data
to the proper byte boundary. It also generates a data valid signal to start
the expected value PRBS generator.
The data shift block uses the shift value from the edge detector to shift the
incoming data stream to the proper byte alignment. The parallel-to-serial-
to-parallel conversion process used in the LVDS transmission can lose the
byte alignment, and this block restores it.
A second receive channel PRBS generator generates the expected values
to compare with the incoming data stream. This generator is identical to
the one used in the transmit channels. The start signal for this generator
comes from the edge detection module.
The compare module takes the output from the data shift block and
compares it with the output from the receive channel PRBS. The 8-bit
words are compared each clock cycle. The comparator output is high if
the words match. The match output from all 15 receive channels is
ANDed together and then stored in a single-bit match register. The
output of this register drives the match LED.