Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 98)

7–16 Quartus II Version 3.0 Altera Corporation
Standard Tests High-Speed Development Kit, Stratix GX Edition User Guide
The design has a Verilog HDL wrapper to name and place all of the pins
and to provide proper termination for the LVDS signals. The Stratix GX
pushbutton switches control the data transmission (start and stop), insert
errors, and reset the circuit. The LEDs indicate the start of transmission,
the start of reception of valid data, confirmation that correct data was
received, error status, and the reset condition.
The main system clock (parallel data rate) is derived from the 33-MHz
crystal oscillator using a 15/4 ratio resulting in 125-MHz clock rate. The
data is generated in 8-bit words per channel using a PRBS generator with
a repetition count of 31, resulting in a serial data rate of 1 Gbps. The data
is then sent to a 2-channel version of the Altera LVDS megafunction,
which uses a high-speed PLL and a SERDES block to convert the data into
serial data streams. The LVDS megafunction also generates the transmit
clock, which is 125 MHz. You can vary the clock speed by changing the
parameters of the LVDS megafunction.
The loopback cables feed the serial data back to the receive inputs on the
Stratix GX device. The data is converted back into parallel by the receive
LVDS megafunction. Because the design used the Stratix GX DPA
feature, the received data byte alignment can be incorrect. Therefore, the
data is sent through a byte alignment and synchronization detection
block. The block looks for the synchronization pattern (the first word of
the PRBS sequence) in the data stream. When it finds this pattern, it shifts
the data as needed and asserts the data valid signal. This assertion
triggers the start of an expected value PRBS generator. The two data
streams are sent to a comparator to generate a match signal on a per
channel basis. If both channels match, the match LED illuminates.
Stratix GX SMA DPA Functional Description
Figure 7–9 shows the Stratix GX DPA logic diagram for the Stratix GX
device. Figure 7–10 shows the Quartus II top-level BDF.
1
Open the BDF in the Quartus II software to view greater detail.