Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 89)

Altera Corporation Quartus II Version 3.0 7–7
Diagnostic Test Details Standard Tests
The data is generated and processed in the following sequence:
■ The data is generated in 8-bit words per channel using a pseudo
random byte sequence (PRBS) generator with a repetition count of
31.
■ The data is then sent to a 16-channel version of the Altera LVDS
megafunction, which uses a high-speed PLL and a
serializer/deserializer (SERDES) block to convert the data into a
serial data stream. The LVDS megafunction also generates the
transmit clock.
■ The data is sent to the Stratix device.
■ The receiver LVDS megafunction converts the serial data back to
parallel.
■ The parallel data is fed back to a transmit block and sent back to the
Stratix GX device as serial data.
■ At the Stratix GX device, the data is converted to parallel.
■ Based on the status channel, the received data is compared to the
output of another PRBS generator. If both data streams match, the
match LED illuminates. Each channel has its own PRBS generator
and comparator. The match LED only illuminates when all channels
match.
This design also includes an error detection and counting block. An error
occurs when data does not match while valid data is transmitted. If an
error occurs, the error LED illuminates and stays on. Every time an error
is detected, the error counter increments and the value displays on the
7-segment display. Pressing the reset turns off the error LED and resets
the counter.
The bridge test has two Quartus II projects:
■ Stratix GX device design—This design has a PLL, an LVDS transmitter
and receiver, and a Verilog HDL block with the logic required to
generate a pseudo-random byte sequence (PRBS) and verify that it
was received correctly.
■ Stratix device design—This design has an LVDS receiver and
transmitter as a loopback implementation.
1
Both devices must be configured with the appropriate design for
the test to work.
The Stratix GX design has a Block Design File (.bdf) as the top-level
design, which allows you to modify the system clock rate as desired to
emulate a particular system configuration. By varying the system clock
PLL and LVDS parameters, you can adjust the per channel data rate from