Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 121)

Altera Corporation Quartus II Version 3.0 7–39
Diagnostic Test Details Nios Designs
The test is a C program that controls a series of PCI bus configuration
transactions. It polls all of the available addresses and monitors the
response. If it finds another board on the bus, it reports the manufacturer
and board type.
Stratix Nios Ethernet, On-Board Flash & EPC16 Flash Test
These designs involve a Nios processor combined with several Avalon
bus arbitration modules to handle all the I/O required to test the on-
board flash memory, the 2 EPC16 configuration devices, and the built-in
Ethernet interface. The design is captured in VHDL and has a VHDL
wrapper to control the I/O pin names and placements. Because this a
processor-based test, the actual test consists of running several object files
on the Nios processor and observing the results in a terminal window on
a PC.
The memory tests perform a series of write, read, and compare cycles.
These cycles write a value to a memory location, read the values back, and
compare the expected value with the value read from the memory. If all
of the values match, the test passes.
The Nios processor tests the on-board LAN91C111 Ethernet MAC/PHY
chip. The test initializes the 10/100 MAC/PHY chip and runs a set of
Ethernet protocol tests using the hello_plugs program, which is a
standard test program for this chip provided with the Nios embedded
processor. The test results vary depending on whether the board is
plugged into a functional network.
f
Refer to “Ethernet, On-Board Flash & EPC16 Flash Interface (Stratix Nios
Ethernet) (Stratix Nios On-Board Flash) (Stratix Nios EPC16 Flash)” on
page 5–25 for information on how to perform the test.
Figure 7–19 shows the Stratix Nios flash memory and Ethernet logic
diagram for the Stratix device.