Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 97)

Altera Corporation Quartus II Version 3.0 7–15
Diagnostic Test Details Standard Tests
The slow speed status channels are controlled in a separate logic block
that is clocked by the system clock at 125 MHz. The data transmitted is
the output from a 4-bit counter. The data is captured in registers and
compared to the expected value. A separate control match LED
illuminates when the data matches.
An LVDS receive megafunction on the Stratix GX device converts the
serial data back to parallel and generates the clock used to regulate the
receive channel logic. The received data is sent through a pattern
detector/data aligner block. When the pattern detector detects the
synchronization pattern twice, it sets the data valid signal and starts
passing the data to the comparator.
A second PRBS generator uses the data valid signal to start generating the
expected data values. This second data set is also sent to the comparator.
The comparator module takes the output from the data aligner block and
compares it with the output from the receive channel PRBS. The 8-bit
words are compared each clock cycle. The comparator output is high if
the words match. The output from all 17 receive channels is ANDed
together and then stored in a single-bit match register that drives the
match LED.
The error detection and counting blocks monitor the match and data
valid signals. If the match signal goes low while data is valid, the error
flag is set and the error counter is incremented. Pressing the reset button
clears the error flag and resets the counter. The error insertion
pushbutton switch inverts one bit in one data channel for one clock cycle,
which is enough to trigger the error detection circuit.
Stratix GX SMA DPA
This section describes the Stratix GX SMA DPA test. Refer to “Source
Synchronous DPA SMA interface (Stratix GX SMA DPA)” on page 5–15
for information on how to perform the test.
Stratix GX SMA DPA Test Overview
The DPA SMA design consists of a PLL, a 2-channel LVDS transmitter
and receiver, and a Verilog HDL block with the logic required to generate
a PRBS and verify that it was received correctly. The design requires 6
SMA cables to complete the signal loopback.
You can use the top-level BDF to modify the system clock rate as desired
to emulate a particular system configuration. By varying the system clock
PLL and LVDS megafunction parameters, you can adjust the per channel
data rate from 300 to 1,000 Mbps. This design uses the DPA feature of the
Stratix GX family to boost the data rate to 1,000 Mbps.