Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 109)

Altera Corporation Quartus II Version 3.0 7–27
Diagnostic Test Details Standard Tests
synchronization data from the GXB megafunction. The data is then
passed to a pattern detection block to find the start of data in the PRBS
(the first word of the PRBS sequence) data stream. When this pattern is
found, the data valid signal is asserted, which triggers an expected value
PRBS generator to start. The two data streams are sent to a comparator to
generate a match signal on a per channel basis. If the data streams match,
the match LED illuminates on a per channel basis. If the match signal goes
low while the data valid signal is high, the error flag is set and the error
counter is incremented. Pressing the reset button resets the system state,
error flag, and error count.
Stratix GX SFP XCVR Functional Description
Figure 7–14 shows the Stratix GX SFP XCVR logic diagram.
Figure 7–14. Stratix GX SFP XCVR Logic Diagram
The GXB megafunction transmit PLL generates the system clock using
the 155.52-MHz crystal oscillator as the reference. The PLL generates a
155.52-MHz clock to clock all of the data generation logic.
PRBS
Generator
ALT GXB
TX
Transmit Channel (x4)
16 1
Start/Stop
Synchronization
Detect/Control 4
8
ALTGXB
RX
Comparator
Receive Channel (x4)
16
16
18
Match
Register
Data Valid
Error
Register
Error
Counter
Data Valid
PRBS
Generator
7-Segment
Display
Error LED
Match LED
Pattern Detect/
Byte Swap
SFP
Connector
Loopback with
Module or Card
SFP Module
Status and Control