Altera High-Speed Development Kit, Stratix GX Edition - Manual (Page 107)

Altera Corporation Quartus II Version 3.0 7–25
Diagnostic Test Details Standard Tests
reset, the seed value is initialized into all registers. This generator
generates the data stream that exercises the system. Each transmit
channel has its own PRBS generator.
The double word option requires synchronization of the control logic
with the GXB receive section. The design uses a 10-bit alignment pattern
(10’h1A7) that permits the internal synchronization of the megafunction
and creates a status signal that is sent to the word swap block in the
control logic. Data transmission can only start when a channel has been
synchronized. Synchronization is done on a per channel basis.
The data from the PRBS generators is sent to the GXB transmit block
created using the Altera MegaWizard Plug-In Manager. The
megafunction is configured as 4 channels running at 3,125 Mbps with an
input clock rate of 156.25 MHz. The signals are then sent to the HM-Zd
XCVR connector (J1) and looped back to the Stratix GX device using the
XCVR HM-Zd loopback card.
1
The design was also tested using the Tyco backplane on the 1-
and 16-inch connections.
When using the long trace connection on the backplane, the receive
equalization must be set for 40 inches for reliable data throughput.
Dipswitches 2 and 1 set the equalization (00 for 0 inches, 01 for 20 inches,
and 11 for 40 inches). The short trace and loopback card work without
equalization.
The receive portion of the GXB megafunction on the Stratix GX device
converts the serial data back to parallel 20-bit words. The received data is
sent through a byte/word swap block that is controlled by the GXB
megafunction, which is required for double word operation because the
alignment pattern is only 10 bits. The data is then passed to the pattern
detector to determine the start of the data packet. When the pattern
detector has detected the synchronization pattern twice, it sets the data
valid signal and starts passing the data to the comparator.
A second PRBS generator uses the data valid signal to start generating the
expected data values. This second data set is also sent to the comparator.
The comparator module takes the output from the pattern detector block
and compares it with the output from the receive channel PRBS. The
20-bit words are compared each clock cycle. The comparator output is
high if the words match. The output from each receive channel
comparator is stored in a single-bit match register. The output of this
register drives the match LED on a per channel basis.