Measurement Computing Analyzer488 - Manual (Page 36)

Section 2 Getting Started
2.14
The first stage of the trigger system is the match comparator stage.
This stage compares the bus state to a specified match state for each bus
event. If a match is detected, this stage sends a signal to the next stage and
also to the CMP output on the Analyzer488 rear panel card edge connector.
The match state is composed of 8 bus data bits, 5 bus management bits, and
1 bit which signifies whether or not a bus error occurred during the event.
Each bit may be set to 0 (unasserted), 1 (asserted), or x (don't care).
The second stage of the trigger system is the match count stage. This
stage counts the number of matches found in the match comparator stage.
When a specified number of matches has occurred, this stage sends a signal
to the next stage.
The third stage of the trigger system is the delay count stage. After
this stage receives a signal from the match count stage, it counts bus events.
When a specified number of bus events has occurred, this stage marks the
trigger point and sends a signal to the next stage and to the trigger output
(the BNC connector) on the rear panel of the Analyzer488.
The fourth stage of the trigger system is the post trigger count stage.
This stage counts the number of bus events occurring after the trigger point.
When a specified number of post trigger events have occurred, the post
trigger count stage generates a signal to the last stage of the trigger system.
The fifth and final stage is the trigger complete stage, which either
disarms the recording system or forces handshaking to Step (leaving
recording enabled) when the required number of post trigger events have
occurred. At this time the trigger system is disabled.
The following illustrations and explanations show three examples
using the trigger system.