Control interface [x1, 11 control interface [x1 – Festo Контроллер двигателя CMMD-AS User Manual

Page 43

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3. Product description

Festo P.BE-CMMD-AS-HW-EN 1002NH

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3.5.11 Control interface [X1]

The control interface [X1] is planned as D-Sub 25-pin. The following signals are available:

Signal:

Description

AMON
AIN0 / #AIN0

Analogue output for monitor purposes
Differential analogue input with 12-bit resolution.
Alternatively, the differential analogue input can be parameterized with the function
Mode and Stop (DIN12 and DIN13, dependent on the parametrised controller interface).

DOUT0 ... DOUT3 Digital outputs with 24 V level,

DOUT0 is permanently occupied with the function "Ready for operation".
Additional outputs can be configured (Motion complete (Target Reached), Axis in
motion, Target speed achieved, ...)

DIN0 ... DIN13 Digital inputs for 24 V level with following functions:

(The inputs are occupied in their function, dependent on the mode selection)

Mode 0
1 x output stage enable (DIN4)
1 x controller enable / acknowledge error (DIN5)
2 x limit switch (DIN6, DIN7)
6 x position selection (DIN0 ... DIN3, DIN10, DIN11)
1 x start positioning (DIN8)
2 x mode shift (DIN9, DIN12)
1 x stop (DIN13)
Mode 1
2 x jog mode (DIN10, DIN11)
1 x teach (DIN8)
Mode 2
1 x halt route program (DIN3)
1 x start route program (DIN8)
2 x next for route program step enabling condition (DIN 2, 11)
Mode 3
2 x pulse/direction (CLK/DIR or CW/CCW on DIN2, DIN3)
1 x start sync (DIN8)

Table 3.13 Control interface [X1]


The digital inputs are designed to be configurable:

Mode 0: Standard assignment

Mode 1: Special assignment for jog/teach operation

Mode 2: Special assignment for the route program

Mode 3: Special assignment for synchronisation

To be able to switch between different I/O configurations, DIN12 and DIN9 can also be
configured as selector signals.
As a result, a maximum of four different I/O assignments can be selected. These are
described in the following tables:

Table 6.2 Pin allocation: I/O interface [X1] mode 0

Table 6.3 Pin allocation: I/O interface [X1] mode 1

Table 6.4 Pin allocation: I/O interface [X1] mode 2

Table 6.5 Pin allocation: I/O interface [X1] mode 3.

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