14 test register, 15 other status signals, 14 test register 8.3.1.15 other status signals – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 139: Table 8-38, Test register, Table 8-39, Other status signals register, Base artm fpga
Base ARTM FPGA
ARTM-831X Installation and Use (6806800M76E)
139
8.3.1.14 Test Register
8.3.1.15 Other Status Signals
Table 8-38 Test Register
Address: 0xE
Bit Description
Default
Access
0
Test Mode
0: normal operation
1: Test mode enabled.
Note: Needed for simulation. Don't set during operation
0
RTM: r/w
1
Configuration SPI Flash SPRL Bit control
0: SPRL bit will be set when the Configuration Update interface is
enabled.
1: SPRL bit will not be set when the Configuration Update
interface is enabled.
0
RTM: r/w
6:2
Reserved
0
r
7
Select Base FPGA Sub-Version.
0: Sub-Version for Base FPGA IP code.
1: Sib-Version for Base Extender FPGA TDM code
0
RTM: r/w
MMC:
r/w
Table 8-39 Other Status Signals Register
Address: 0xF
Bit Description
Default
Access
0
Level of RTM_HEALTHY
ext.
RTM: r
MMC: r
7:1
Reserved
0
r