Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 323)

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ARTM-831X Installation and Use (6806800M76E) 323
The bits of this register mask the bits of the Xrt75LineEvtReg for the generation of an interrupt
to the host.
Bit Acronym Type Description Default Pwr Soft
31...22 - - reserved undef - -
21 Xrt75TrmDmoIntrptMas
k5 RW 0b1:
Xrt75TrmDmoIntrptEnable5,
enables Transmitter Drive
Monitor of line 5 interrupt 0b0 X X
20 Xrt75TrmDmoIntrptMas
k4 RW 0b1:
Xrt75TrmDmoIntrptEnable4,
enables Transmitter Drive
Monitor of line 4 interrupt 0b0 X X
19 Xrt75TrmDmoIntrptMas
k3 RW 0b1:
Xrt75TrmDmoIntrptEnable3,
enables Transmitter Drive
Monitor of line 3 interrupt 0b0 X X
18 Xrt75TrmDmoIntrptMas
k2 RW 0b1:
Xrt75TrmDmoIntrptEnable2,
enables Transmitter Drive
Monitor of line 2 interrupt 0b0 X X
17 Xrt75TrmDmoIntrptMas
k1 RW 0b1:
Xrt75TrmDmoIntrptEnable1,
enables Transmitter Drive
Monitor of line 1 interrupt 0b0 X X
16 Xrt75TrmDmoIntrptMas
k0 RW 0b1:
Xrt75TrmDmoIntrptEnable0,
enables Transmitter Drive
Monitor of line 0 interrupt 0b0 X X
15...14 - - reserved undef - -
13 Xrt75RcvLoLIntrptMask5 RW 0b1:
Xrt75RcvLoLIntrptEnable5,
resets Receiver Line 5
indicates loss of lock
interrupt bit 0b0 X X