Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 203)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 203
6 SerDesCltConf2RegC
opy RW 0b0: SerDesCltConf2RegCopy, when
set, a value written to any SerDes client
register is discarded, but all SerDes
client registers are initialized as
specified in the Fpga configuration
bitstream. Values are copied from
background configuration memory to
SerDes client registers. 0b0 X X
5 - - reserved undef - -
4...
3 QuadAddr RW Quad Address
0x0: QuadDspSubMod0And1, selects
the Quad where Dsp Fpga Submodule 0
and 1 are connected to.
0x1: QuadDspBase, selects the Quad
where Dsp Fpga on Baseboard is
connected to.
0x2: reserved
0x3: QuadPcie, selects the Quad the
PciExpress interface is connected to.
0x0 X X
2...
0 ChanAddr RW Channel Address
0x0: ChanDspSubMod0, selects
channel for DspSubMod0
0x0: ChanDspBase, selects channel for
DspBase
0x0: ChanPcie, selects channel for Pcie
0x1: reserved
0x2: ChanDspSubMod1, selects
channel for DspSubMod1
0x3: reserved
0x4: ChanAux, selects auxiliary channel
for access of quad wise registers
0x5: reserved
0x6: reserved
0x7: reserved
0x0 X X
Bit Acronym Type
Description
Default
Pwr Soft