Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 270)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 270
15 Xrt86Chp1RcvLoS7 R 0b1: Xrt86Chp1RcvLoS7,
Chip 1 receiver Line 7
indicates loss of signal 0b0 F F
14 Xrt86Chp1RcvLoS6 R 0b1: Xrt86Chp1RcvLoS6,
Chip 1 receiver Line 6
indicates loss of signal 0b0 F F
13 Xrt86Chp1RcvLoS5 R 0b1: Xrt86Chp1RcvLoS5,
Chip 1 receiver Line 5
indicates loss of signal 0b0 F F
12 Xrt86Chp1RcvLoS4 R 0b1: Xrt86Chp1RcvLoS4,
Chip 1 receiver Line 4
indicates loss of signal 0b0 F F
11 Xrt86Chp1RcvLoS3 R 0b1: Xrt86Chp1RcvLoS3,
Chip 1 receiver Line 3
indicates loss of signal 0b0 F F
10 Xrt86Chp1RcvLoS2 R 0b1: Xrt86Chp1RcvLoS2,
Chip 1 receiver Line 2
indicates loss of signal 0b0 F F
9 Xrt86Chp1RcvLoS1 R 0b1: Xrt86Chp1RcvLoS1,
Chip 1 receiver Line 1
indicates loss of signal 0b0 F F
8 Xrt86Chp1RcvLoS0 R 0b1: Xrt86Chp1RcvLoS0,
Chip 1 receiver Line 0
indicates loss of signal 0b0 F F
7 Xrt86Chp0RcvLoS7 R 0b1: Xrt86Chp0RcvLoS7,
Chip 2 receiver Line 7
indicates loss of signal 0b0 F F
6 Xrt86Chp0RcvLoS6 R 0b1: Xrt86Chp0RcvLoS6,
Chip 2 receiver Line 6
indicates loss of signal 0b0 F F
5 Xrt86Chp0RcvLoS5 R 0b1: Xrt86Chp0RcvLoS5,
Chip 2 receiver Line 5
indicates loss of signal 0b0 F F
4 Xrt86Chp0RcvLoS4 R 0b1: Xrt86Chp0RcvLoS4,
Chip 2 receiver Line 4
indicates loss of signal 0b0 F F
Bit Acronym Type Description Default Pwr Soft