1 general register (gnrlregs), Ext fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 301

EXT FPGA
ARTM-831X Installation and Use (6806800M76E)
301
undef = undefined or
const = containing a constant value not affected by any reset.
Columns right of the default column contain a reset cause in the header row of the table and in
the table itself:.
- = bits are not affected by this reset
X = bits are set immediately to default value by this reset
F = bits are set to default value by connected function when this reset occurs
Reserved Bits within registers have an undefined value when read and should be written as read
before when written.
Reserved values:
* = all values of this bit/nibble position are reserved combinations
r = remaining not previously noted combinations of this bit/nibble positions are reserved
values
It is forbidden to write reserved combinations to registers.
[Hw: ...........] = Supplementary information about HW implementation, for HW review
purposes only.
10.4.2.1 General Register (GnrlRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
Collection of general register not dedicated to particular functions.
10.4.2.1.1 Soft Reset Register
Address:
0x0, SoftResReg