Ext fpga – Artesyn ARTM-831X Installation and Use (June 2014) User Manual
Page 321

EXT FPGA
ARTM-831X Installation and Use (6806800M76E)
321
12
Xrt75RcvLoLIntrptReset4
RW
0b1:
Xrt75RcvLoLIntrptReset4,
resets Receiver Line 4
indicates loss of lock
indicator bit
0b0
X
X
11
Xrt75RcvLoLIntrptReset3
RW
0b1:
Xrt75RcvLoLIntrptReset3,
resets Receiver Line 3
indicates loss of lock
indicator bit
0b0
X
X
10
Xrt75RcvLoLIntrptReset2
RW
0b1:
Xrt75RcvLoLIntrptReset2,
resets Receiver Line 2
indicates loss of lock
indicator bit
0b0
X
X
9
Xrt75RcvLoLIntrptReset1
RW
0b1:
Xrt75RcvLoLIntrptReset1,
resets Receiver Line 1
indicates loss of lock
indicator bit
0b0
X
X
8
Xrt75RcvLoLIntrptReset0
RW
0b1:
Xrt75RcvLoLIntrptReset0,
resets Receiver Line 0
indicates loss of lock
indicator bit
0b0
X
X
7...6
-
-
reserved
undef
-
-
5
Xrt75RcvLoSIntrptReset5
RW
0b1:
Xrt75RcvLoSIntrptReset5,
resets Receiver Line 5
indicates loss of signal
indictor bit
0b0
X
X
4
Xrt75RcvLoSIntrptReset4
RW
0b1:
Xrt75RcvLoSIntrptReset4,
resets Receiver Line 4
indicates loss of signal
indictor bit
0b0
X
X
Bit
Acronym
Type
Description
Default
Pwr
Soft