Artesyn ARTM-831X Installation and Use (June 2014) - Manual (Page 265)

TSI FPGA
ARTM-831X Installation and Use (6806800M76E) 265
9.5.2.13 Framer and Line Interface Unit Sideband Signal Registers
(FrLiuSdBndRegs)
Resets:
Pwr = Power on reset
Soft = Soft reset
Registers to control, control further processing or monitor signals of PMC8310-, XRT86-
framers chip 0 and 1 and XRT75 Line interfaces
9.5.2.13.1 SelectRcvrdLclk
Addresses:
0x1600, SelRclk0
0x1604, SelRclk1
Width: 32 bit
The registers control which of 8 recovered line clocks from XRT86 framer chips 0 and 1 or which
of 8 (4 SDH, 4 E1T1) recovered line clocks from upto 2 PMC8310 line framers is switched to the
respective RtmRLClk0 or RtmRtmFpgaRLClk1output of the RtmFpga (SelRclk0 determines
RtmRtmFpgaRLClk0, SelRclk0 determines RtmRtmFpgaRLClk1. The RtmRtmFpgaRLClk0 and 1
are connected to the ExtFPGA on the front board which finally decides which RCLK 0 and 1 to
put for synchronization to the central TDM clock generator.